Issued Patents All Time
Showing 101–125 of 197 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9240448 | Bipolar junction transistors with reduced base-collector junction capacitance | James W. Adkisson, James R. Elliott, David L. Harame, Marwan H. Khater, Robert K. Leidy +1 more | 2016-01-19 |
| 9236499 | Junction field-effect transistor with raised source and drain regions formed by selective epitaxy | Kevin K. Chan, John J. Ellis-Monaghan, David L. Harame, John J. Pekarik | 2016-01-12 |
| 9231087 | Bipolar junction transistors with self-aligned terminals | John Benoit, James R. Elliott, Peter B. Gray, Alvin J. Joseph, Christa R. Willets | 2016-01-05 |
| 9231089 | Formation of an asymmetric trench in a semiconductor substrate and a bipolar semiconductor device having an asymmetric trench isolation region | Robert K. Leidy, Mark D. Levy, Gary L. Milo | 2016-01-05 |
| 9224843 | Formation of a high aspect ratio trench in a semiconductor substrate and a bipolar semiconductor device having a high aspect ratio trench isolation region | John Benoit, James R. Elliott | 2015-12-29 |
| 9224841 | Semiconductor fins on a trench isolation region in a bulk semiconductor substrate and a method of forming the semiconductor fins | David L. Harame, Edward J. Nowak | 2015-12-29 |
| 9202900 | Method to bridge extrinsic and intrinsic base by selective epitaxy in BiCMOS technology | James W. Adkisson, Kevin K. Chan, David L. Harame, John J. Pekarik | 2015-12-01 |
| 9202869 | Self-aligned bipolar junction transistor having self-planarizing isolation raised base structures | Natalie B. Feilchenfeld | 2015-12-01 |
| 9159816 | PNP bipolar junction transistor fabrication using selective epitaxy | David L. Harame | 2015-10-13 |
| 9159801 | Bipolar junction transistor with multiple emitter fingers | Renata Camillo-Castillo, David L. Harame, Ramana Malladi, John J. Pekarik | 2015-10-13 |
| 9111986 | Self-aligned emitter-base-collector bipolar junction transistors with a single crystal raised extrinsic base | Renata Camillo-Castillo, Peng Cheng, Vibhor Jain, John J. Pekarik | 2015-08-18 |
| 9105677 | Base profile of self-aligned bipolar transistors for power amplifier applications | James S. Dunn, James S. Nakos | 2015-08-11 |
| 9093478 | Integrated circuit structure with bulk silicon FinFET and methods of forming | Kangguo Cheng, Ali Khakifirooz, Edward J. Nowak, Jed H. Rankin | 2015-07-28 |
| 9093491 | Bipolar junction transistors with reduced base-collector junction capacitance | James W. Adkisson, James R. Elliott, David L. Harame, Marwan H. Khater, Robert K. Leidy +1 more | 2015-07-28 |
| 9087868 | Bipolar junction transistors with self-aligned terminals | — | 2015-07-21 |
| 9059252 | Silicon waveguide on bulk silicon substrate and methods of forming | Steven M. Shank | 2015-06-16 |
| 9059196 | Bipolar junction transistors with self-aligned terminals | John Benoit, James R. Elliot, Peter B. Gray, Alvin J. Joseph, Christa R. Willets | 2015-06-16 |
| 9059138 | Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure | Renata Camillo-Castillo, Zhong-Xiang He, Jeffrey B. Johnson, Xuefeng Liu | 2015-06-16 |
| 9059233 | Formation of an asymmetric trench in a semiconductor substrate and a bipolar semiconductor device having an asymmetric trench isolation region | Robert K. Leidy, Mark D. Levy, Gary L. Milo | 2015-06-16 |
| 9059234 | Formation of a high aspect ratio trench in a semiconductor substrate and a bipolar semiconductor device having a high aspect ratio trench isolation region | John Benoit, James R. Elliott | 2015-06-16 |
| 9053939 | Heterojunction bipolar transistor with epitaxial emitter stack to improve vertical scaling | Thomas N. Adam, David L. Harame, Alexander Reznicek | 2015-06-09 |
| 9041105 | Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure | William F. Clark, Jr., Robert M. Rassel, Yun Shi | 2015-05-26 |
| 9029229 | Semiconductor device and method of forming the device by forming monocrystalline semiconductor layers on a dielectric layer over isolation regions | James W. Adkisson, Peng Cheng, Vibhor Jain, Vikas K. Kaushal, John J. Pekarik | 2015-05-12 |
| 9029949 | Semiconductor-on-insulator (SOI) structures with local heat dissipater(s) and methods | Jeffrey P. Gambino, Zhenzhen Ye, Yan Zhang | 2015-05-12 |
| 9018754 | Heat dissipative electrical isolation/insulation structure for semiconductor devices and method of making | Jeffrey P. Gambino, Zhenzhen Ye, Yan Zhang | 2015-04-28 |