Issued Patents All Time
Showing 51–75 of 197 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10090391 | Tunable breakdown voltage RF FET devices | Vibhor Jain, John J. Pekarik | 2018-10-02 |
| 10038063 | Tunable breakdown voltage RF FET devices | Vibhor Jain, John J. Pekarik | 2018-07-31 |
| 10014397 | Bipolar junction transistors with a combined vertical-lateral architecture | Vibhor Jain, David L. Harame, Renata Camillo-Castillo | 2018-07-03 |
| 9947573 | Lateral PiN diodes and schottky diodes | Natalie B. Feilchenfeld, Vibhor Jain | 2018-04-17 |
| 9917005 | Semiconductor structure with airgap | Mark D. Jaffe, Alvin J. Joseph, Anthony K. Stamper | 2018-03-13 |
| 9899375 | Co-integration of self-aligned and non-self aligned heterojunction bipolar transistors | Vibhor Jain | 2018-02-20 |
| 9847408 | Fabrication of integrated circuit structures for bipolor transistors | Vibhor Jain | 2017-12-19 |
| 9837514 | Vertical P-type, N-type, P-type (PNP) junction integrated circuit (IC) structure | Joseph R. Greco, Aaron L. Vallett, Robert F. Vatter | 2017-12-05 |
| 9818688 | Dielectric region in a bulk silicon substrate providing a high-Q passive resonator | James S. Dunn, Zhong-Xiang He | 2017-11-14 |
| 9799720 | Inductor heat dissipation in an integrated circuit | Jeffrey P. Gambino, Zhenzhen Ye, Yan Zhang | 2017-10-24 |
| 9799693 | Photodetector and method of forming the photodetector on stacked trench isolation regions | John J. Ellis-Monaghan, Steven M. Shank | 2017-10-24 |
| 9759868 | Structures for preventing dicing damage | Brett T. Cucci, Paul F. Fortier, Jeffrey P. Gambino, Robert K. Leidy, Richard J. Rassel | 2017-09-12 |
| 9735259 | Method to build vertical PNP in a BiCMOS technology with improved speed | Joseph R. Greco, Aaron L. Vallett, Robert F. Vatter | 2017-08-15 |
| 9726547 | Microbolometer devices in CMOS and BiCMOS technologies | Anthony K. Stamper, Ronald F. Waller | 2017-08-08 |
| 9721949 | Method of forming super steep retrograde wells on FinFET | Xusheng Wu, David L. Harame, Renata Camillo-Castillo | 2017-08-01 |
| 9703036 | Optoelectronic structures having multi-level optical waveguides and methods of forming the structures | Zhong-Xiang He, Ronald G. Meunier, Steven M. Shank | 2017-07-11 |
| 9666475 | Semiconductor structure with airgap | Mark D. Jaffe, Alvin J. Joseph, Anthony K. Stamper | 2017-05-30 |
| 9653477 | Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming | Peng Cheng, James S. Dunn, Blaine J. Gross, James A. Slinkman | 2017-05-16 |
| 9646993 | Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming | Peng Cheng, James S. Dunn, Blaine J. Gross, James A. Slinkman | 2017-05-09 |
| 9633894 | Semiconductor structure with airgap | Mark D. Jaffe, Alvin J. Joseph, Anthony K. Stamper | 2017-04-25 |
| 9608096 | Implementing stress in a bipolar junction transistor | Renata Camillo-Castillo, Vibhor Jain, James W. Adkisson, David L. Harame | 2017-03-28 |
| 9590082 | Integration of heterojunction bipolar transistors with different base profiles | Vibhor Jain | 2017-03-07 |
| 9576899 | Electrical fuse with high off resistance | Vibhor Jain, Ian McCallum-Cook | 2017-02-21 |
| 9570564 | Self-aligned emitter-base bipolar junction transistor with reduced base resistance and base-collector capacitance | Deborah A. Alperstein, David L. Harame, Alvin J. Joseph, Keith J. Machia, Christa R. Willets | 2017-02-14 |
| 9564508 | Device isolation with improved thermal conductivity | Mattias E. Dahlstrom, Dinh Dang, Ramana Malladi | 2017-02-07 |