Issued Patents All Time
Showing 76–100 of 581 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10944012 | Area-efficient inverter using stacked vertical transistors | Alexander Reznicek, Kangguo Cheng, Karthik Balakrishnan | 2021-03-09 |
| 10943903 | Asymmetric threshold voltage VTFET with intrinsic dual channel epitaxy | Choonghyun Lee, Jingyun Zhang, Takashi Ando, Alexander Reznicek | 2021-03-09 |
| 10943787 | Confined work function material for gate-all around transistor devices | Jingyun Zhang, Choonghyun Lee, Takashi Ando, Alexander Reznicek | 2021-03-09 |
| 10942072 | Nanoscale magnetic tunnel junction arrays for sub-micrometer resolution pressure sensor | Chandrasekharan Kothandaraman, Eric Raymond Evarts, Virat Vasav Mehta, Alexander Reznicek | 2021-03-09 |
| 10937903 | Twin gate field effect diode | Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek | 2021-03-02 |
| 10937898 | Lateral bipolar junction transistor with dual base region | Bahman Hekmatshoartabari, Alexander Reznicek, Karthik Balakrishnan, Jeng-Bang Yau | 2021-03-02 |
| 10937883 | Vertical transport FETs having a gradient threshold voltage | Choonghyun Lee, Takashi Ando, Jingyun Zhang, Alexander Reznicek | 2021-03-02 |
| 10937863 | Fabrication of perfectly symmetric gate-all-around FET on suspended nanowire using interface interaction | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2021-03-02 |
| 10937828 | Fabricating embedded magnetoresistive random access memory device with v-shaped magnetic tunnel junction profile | Matthias Georg Gottwald, Alexander Reznicek, Chandrasekharan Kothandaraman | 2021-03-02 |
| 10930779 | Method of forming a vertical transistor pass gate device | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2021-02-23 |
| 10930762 | Multiple work function nanosheet field effect transistor using sacrificial silicon germanium growth | Takashi Ando, Choonghyun Lee | 2021-02-23 |
| 10923403 | Co-integration of high carrier mobility PFET and NFET devices on the same substrate using low temperature condensation | Takashi Ando, Choonghyun Lee | 2021-02-16 |
| 10916432 | Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device | Takashi Ando, Hemanth Jagannathan, Choonghyun Lee, Vijay Narayanan | 2021-02-09 |
| 10916659 | Asymmetric threshold voltage FinFET device by partial channel doping variation | Alexander Reznicek, Choonghyun Lee, Takashi Ando, Jingyun Zhang | 2021-02-09 |
| 10903417 | MTJ containing device with replacement top electrode | Alexander Reznicek, Nathan P. Marchack, Bruce B. Doris | 2021-01-26 |
| 10903210 | Sub-fin doped bulk fin field effect transistor (FinFET), Integrated Circuit (IC) and method of manufacture | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2021-01-26 |
| 10896965 | Formation of wrap-around-contact to reduce contact resistivity | Adra Carr, Jingyun Zhang, Choonghyun Lee, Takashi Ando | 2021-01-19 |
| 10896962 | Asymmetric threshold voltages in semiconductor devices | Takashi Ando, Alexander Reznicek, Jingyun Zhang, Choonghyun Lee | 2021-01-19 |
| 10892403 | Structured bottom electrode for MTJ containing devices | Nathan P. Marchack, Bruce B. Doris | 2021-01-12 |
| 10886376 | Formation of wrap-around-contact to reduce contact resistivity | Adra Carr, Jingyun Zhang, Choonghyun Lee, Takashi Ando | 2021-01-05 |
| 10886369 | Formation of self-limited inner spacer for gate-all-around nanosheet FET | Jingyun Zhang, Takashi Ando, Choonghyun Lee, Alexander Reznicek | 2021-01-05 |
| 10879311 | Vertical transport Fin field effect transistors combined with resistive memory structures | Choonghyun Lee, Takashi Ando, Alexander Reznicek, Jingyun Zhang | 2020-12-29 |
| 10879352 | Vertically stacked nFETs and pFETs with gate-all-around structure | Jingyun Zhang, Takashi Ando, Choonghyun Lee, Alexander Reznicek | 2020-12-29 |
| 10840433 | MRAM with high-aspect ratio bottom electrode | Bruce B. Doris, John A. Ott, Nathan P. Marchack | 2020-11-17 |
| 10833181 | Single column compound semiconductor bipolar junction transistor with all-around base | Karthik Balakrishnan, Tak H. Ning, Alexander Reznicek | 2020-11-10 |