Issued Patents All Time
Showing 101–125 of 581 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10825921 | Lateral bipolar junction transistor with controlled junction | Karthik Balakrishnan, Tak H. Ning, Alexander Reznicek | 2020-11-03 |
| 10804382 | Integrated ferroelectric capacitor/field effect transistor structure | Takashi Ando, Alexander Reznicek | 2020-10-13 |
| 10804278 | High density programmable e-fuse co-integrated with vertical FETs | Karthik Balakrishnan, Michael A. Guillorn, Alexander Reznicek | 2020-10-13 |
| 10790001 | Tapered VA structure for increased alignment tolerance and reduced sputter redeposition in MTJ devices | Bruce B. Doris, Nathan P. Marchack | 2020-09-29 |
| 10790357 | VFET with channel profile control using selective GE oxidation and drive-out | Takashi Ando, Alexander Reznicek, Jingyun Zhang, Choonghyun Lee | 2020-09-29 |
| 10784347 | High-performance lateral BJT with epitaxial lightly doped intrinsic base | Tak H. Ning, Jeng-Bang Yau | 2020-09-22 |
| 10770461 | Enhanced field resistive RAM integrated with nanosheet technology | Takashi Ando, Alexander Reznicek | 2020-09-08 |
| 10770652 | Magnetic tunnel junction (MTJ) bilayer hard mask to prevent redeposition | Nathan P. Marchack, Bruce B. Doris | 2020-09-08 |
| 10763177 | I/O device for gate-all-around transistors | Jingyun Zhang, Takashi Ando, Choonghyun Lee, Alexander Reznicek | 2020-09-01 |
| 10756176 | Stacked nanosheet technology with uniform Vth control | Takashi Ando, Jingyun Zhang, Choonghyun Lee, Alexander Reznicek | 2020-08-25 |
| 10748990 | Stacked indium gallium arsenide nanosheets on silicon with bottom trapezoid isolation | Takashi Ando, Mahmoud Khojasteh, Alexander Reznicek | 2020-08-18 |
| 10748994 | Vertically stacked nFET and pFET with dual work function | Alexander Reznicek, Takashi Ando, Jingyun Zhang, Choonghyun Lee | 2020-08-18 |
| 10748819 | Vertical transport FETs with asymmetric channel profiles using dipole layers | Takashi Ando, Choonghyun Lee, Sanghoon Shin, Jingyun Zhang, Alexander Reznicek | 2020-08-18 |
| 10734286 | Multiple dielectrics for gate-all-around transistors | Takashi Ando, Jingyun Zhang, Alexander Reznicek, Choonghyun Lee | 2020-08-04 |
| 10734382 | Method for manufacturing a semiconductor structure including a very narrow aspect ratio trapping trench structure | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2020-08-04 |
| 10734505 | Lateral bipolar junction transistor with dual base region | Bahman Hekmatshoartabari, Alexander Reznicek, Karthik Balakrishnan, Jeng-Bang Yau | 2020-08-04 |
| 10734447 | Field-effect transistor unit cells for neural networks with differential weights | Takashi Ando, Alexander Reznicek, Choonghyun Lee, Jingyun Zhang | 2020-08-04 |
| 10734479 | FinFET CMOS with asymmetric gate threshold voltage | Alexander Reznicek, Choonghyun Lee, Takashi Ando, Jingyun Zhang | 2020-08-04 |
| 10727299 | Lateral bipolar junction transistor with abrupt junction and compound buried oxide | Kevin K. Chan, Tak H. Ning, Alexander Reznicek | 2020-07-28 |
| 10727310 | Contact formation on germanium-containing substrates using hydrogenated silicon | Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek | 2020-07-28 |
| 10720528 | Method and structure of stacked FinFET | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2020-07-21 |
| 10720427 | Diode connected vertical transistor | Karthik Balakrishnan, Alexander Reznicek | 2020-07-21 |
| 10720502 | Vertical transistors having a layer of charge carriers in the extension region for reduced extension region resistance | Takashi Ando, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang | 2020-07-21 |
| 10714593 | Fabrication of strained vertical p-type field effect transistors by bottom condensation | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2020-07-14 |
| 10714570 | Fabrication of perfectly symmetric gate-all-around FET on suspended nanowire using interface interaction | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2020-07-14 |