Issued Patents All Time
Showing 476–500 of 581 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9508851 | Formation of bulk SiGe fin with dielectric isolation by anodization | Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2016-11-29 |
| 9502243 | Multi-orientation SOI substrates for co-integration of different conductivity type semiconductor devices | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2016-11-22 |
| 9502245 | Elimination of defects in long aspect ratio trapping trench structures | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2016-11-22 |
| 9496260 | Tall strained high percentage silicon germanium fins for CMOS | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2016-11-15 |
| 9496401 | III-V device structure with multiple threshold voltage | Kangguo Cheng, Keith E. Fogel, Alexander Reznicek | 2016-11-15 |
| 9496400 | FinFET with stacked faceted S/D epitaxy for improved contact resistance | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2016-11-15 |
| 9496373 | Damage-resistant fin structures and FinFET CMOS | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2016-11-15 |
| 9496263 | Stacked strained and strain-relaxed hexagonal nanowires | Takashi Ando, John A. Ott, Alexander Reznicek | 2016-11-15 |
| 9490332 | Atomic layer doping and spacer engineering for reduced external resistance in finFETs | Karthik Balakrishnan, Kevin K. Chan | 2016-11-08 |
| 9490161 | Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same | Bruce B. Doris, Lisa F. Edge, Alexander Reznicek | 2016-11-08 |
| 9484405 | Stacked nanowire devices formed using lateral aspect ratio trapping | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2016-11-01 |
| 9484412 | Strained silicon—germanium integrated circuit with inversion capacitance enhancement and method to fabricate same | Takashi Ando, Pranita Kerber, Alexander Reznicek | 2016-11-01 |
| 9483592 | Maintaining stress in a layout design of an integrated circuit having fin-type field-effect transistor devices | Karthik Balakrishnan, Jeffrey W. Sleight, Tenko Yamashita | 2016-11-01 |
| 9484266 | Complementary heterogeneous MOSFET using global SiGe substrate and hard-mask memorized germanium dilution for nFET | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2016-11-01 |
| 9478642 | Semiconductor junction formation | Shogo Mochizuki, Alexander Reznicek, Dominic J. Schepis | 2016-10-25 |
| 9472628 | Heterogeneous source drain region and extension region | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2016-10-18 |
| 9472671 | Method and structure for forming dually strained silicon | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2016-10-18 |
| 9472460 | Uniform depth fin trench formation | Alexander Reznicek, Kangguo Cheng, Ali Khakifirooz, Dominic J. Schepis | 2016-10-18 |
| 9472471 | Hybrid orientation vertically stacked III-V and Ge gate-all-around CMOS | Karthik Balakrishnan, Sanghoon Lee, Alexander Reznicek | 2016-10-18 |
| 9472555 | Nanosheet CMOS with hybrid orientation | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2016-10-18 |
| 9472575 | Formation of strained fins in a finFET device | Ali Khakifirooz, Alexander Reznicek | 2016-10-18 |
| 9472573 | Silicon-germanium fin formation | Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2016-10-18 |
| 9466567 | Nanowire compatible E-fuse | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2016-10-11 |
| 9466672 | Reduced defect densities in graded buffer layers by tensile strained interlayers | Kangguo Cheng, Keith E. Fogel, John A. Ott, Alexander Reznicek | 2016-10-11 |
| 9466690 | Precisely controlling III-V height | Karthik Balakrishnan, Kangguo Cheng, Alexander Reznicek | 2016-10-11 |