Issued Patents All Time
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6767781 | Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask | Jonathan E. Faltermeier, Ramachandra Divakaruni, Wolfgang Bergner | 2004-07-27 |
| 6727539 | Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect | Ramachandra Divakaruni, Ulrike Gruening, Jack A. Mandelman, Carl Radens | 2004-04-27 |
| 6713835 | Method for manufacturing a multi-level interconnect structure | David V. Horak, Charles W. Koburger, III, Peter H. Mitchell | 2004-03-30 |
| 6686668 | Structure and method of forming bitline contacts for a vertical DRAM array using a line bitline contact mask | Johnathan E. Faltermeier, Ramachandra Divakaruni, Wolfgang Bergner | 2004-02-03 |
| 6620676 | Structure and methods for process integration in vertical DRAM cell fabrication | Rajeev Malik, Jochen Beintner, Rama Divakaruni | 2003-09-16 |
| 6573137 | Single sided buried strap | Ramachandra Divakaruni, Jack A. Mandelman, Wolfgang Bergner, Gary B. Bronner, Ulrike Gruening +5 more | 2003-06-03 |
| 6541810 | Modified vertical MOSFET and methods of formation thereof | Ramachandra Divakaruni, Prakash Dev, Rajeev Malik | 2003-04-01 |
| 6509624 | Semiconductor fuses and antifuses in vertical DRAMS | Carl Radens, Wolfgang Bergner, Rama Divakaruni | 2003-01-21 |
| 6429068 | Structure and method of fabricating embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect | Ramachandra Divakaruni, Ulrike Gruening, Jack A. Mandelman, Carl Radens | 2002-08-06 |
| 6309924 | Method of forming self-limiting polysilicon LOCOS for DRAM cell | Ramachandra Divakaruni, Jack A. Mandelman, Irene McStay, Carl Radens, Helmut Tews | 2001-10-30 |
| 6245651 | Method of simultaneously forming a line interconnect and a borderless contact to diffusion | Rama Divakaruni, Carl Radens | 2001-06-12 |
| 6184107 | Capacitor trench-top dielectric for self-aligned device isolation | Rama Divakaruni, Ulrike Gruening, Byeong Y. Kim, Jack A. Mandelman, Carl Radens | 2001-02-06 |
| 6084276 | Threshold voltage tailoring of corner of MOSFET device | Jeffrey P. Gambino, Gary B. Bronner, Jack A. Mandelman | 2000-07-04 |
| 5994202 | Threshold voltage tailoring of the corner of a MOSFET device | Jeffrey P. Gambino, Gary B. Bronner, Jack A. Mandelman | 1999-11-30 |
| 5923991 | Methods to prevent divot formation in shallow trench isolation areas | Gary B. Bronner, Jeffrey P. Gambino | 1999-07-13 |
| 4398341 | Method of fabricating a highly conductive structure | Henry J. Geipel, Jr. | 1983-08-16 |