Issued Patents All Time
Showing 226–250 of 316 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9761587 | Tall strained high percentage silicon germanium fins for CMOS | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-09-12 |
| 9754933 | Large area diode co-integrated with vertical field-effect-transistors | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-09-05 |
| 9748385 | Method for forming vertical Schottky contact FET | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-08-29 |
| 9748098 | Controlled confined lateral III-V epitaxy | Lukas Czornomaz, Pouya Hashemi, Alexander Reznicek | 2017-08-29 |
| 9734344 | Providing control in a multi user environment | Balasubrahmanyam Gattu, Hashir Khan | 2017-08-15 |
| 9735176 | Stacked nanowires with multi-threshold voltage solution for PFETS | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-08-15 |
| 9735258 | Nanowire semiconductor device | Pouya Hashemi, Sanghoon Lee | 2017-08-15 |
| 9728542 | High density programmable e-fuse co-integrated with vertical FETs | Michael A. Guillorn, Pouya Hashemi, Alexander Reznicek | 2017-08-08 |
| 9726634 | Superhydrophobic electrode and biosensing device using the same | Ali Afzali-Ardakani, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek | 2017-08-08 |
| 9719991 | Devices for detecting a particle in a sample and methods for use thereof | Lydia Lee Sohn, George Anwar, Matthew Rowe Chapman | 2017-08-01 |
| 9722048 | Vertical transistors with reduced bottom electrode series resistance | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-08-01 |
| 9721970 | Gate all-around FinFET device and a method of manufacturing same | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-08-01 |
| 9716145 | Strained stacked nanowire field-effect transistors (FETs) | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-07-25 |
| 9716173 | Compressive strain semiconductor substrates | Pouya Hashemi, Nicolas Loubet, Alexander Reznicek | 2017-07-25 |
| 9716155 | Vertical field-effect-transistors having multiple threshold voltages | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-07-25 |
| 9702924 | Simultaneously measuring degradation in multiple FETs | Keith A. Jenkins, Christos Vezyrtzis | 2017-07-11 |
| 9702841 | Devices and methods using swipe detection | Kanishk Parashar, Bret Foreman, Rory Nordeen | 2017-07-11 |
| 9704860 | Epitaxial oxide fin segments to prevent strained semiconductor fin end relaxation | Keith E. Fogel, Sivananda K. Kanakasabapathy, Alexander Reznicek | 2017-07-11 |
| 9698145 | Implementation of long-channel thick-oxide devices in vertical transistor flow | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-07-04 |
| 9691715 | Support for long channel length nanowire transistors | Isaac Lauer, Tenko Yamashita, Jeffrey W. Sleight | 2017-06-27 |
| 9691854 | Semiconductor device including multiple fin heights | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-06-27 |
| 9684753 | Techniques for generating nanowire pad data from pre-existing design data | Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight | 2017-06-20 |
| 9685510 | SiGe CMOS with tensely strained NFET and compressively strained PFET | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-06-20 |
| 9685409 | Top metal contact for vertical transistor structures | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-06-20 |
| 9666669 | Superlattice lateral bipolar junction transistor | Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek | 2017-05-30 |