Issued Patents All Time
Showing 276–300 of 316 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9536939 | High density vertically integrated FEOL MIM capacitor | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2017-01-03 |
| 9536795 | Multiple threshold voltage trigate devices using 3D condensation | Pouya Hashemi | 2017-01-03 |
| 9530772 | Methods of manufacturing devices including gates with multiple lengths | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-12-27 |
| 9530669 | Method of making a semiconductor device having a semiconductor material on a relaxed semiconductor including replacing a strained, selective etchable material, with a low density dielectric in a cavity | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-12-27 |
| 9524969 | Integrated circuit having strained fins on bulk substrate | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-12-20 |
| 9525064 | Channel-last replacement metal-gate vertical field effect transistor | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-12-20 |
| 9520469 | Fabrication of fin structures having high germanium content | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-12-13 |
| 9515194 | Nano-ribbon channel transistor with back-bias control | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-12-06 |
| 9496260 | Tall strained high percentage silicon germanium fins for CMOS | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-11-15 |
| 9496400 | FinFET with stacked faceted S/D epitaxy for improved contact resistance | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-11-15 |
| 9490332 | Atomic layer doping and spacer engineering for reduced external resistance in finFETs | Kevin K. Chan, Pouya Hashemi | 2016-11-08 |
| 9484405 | Stacked nanowire devices formed using lateral aspect ratio trapping | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-11-01 |
| 9484266 | Complementary heterogeneous MOSFET using global SiGe substrate and hard-mask memorized germanium dilution for nFET | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-11-01 |
| 9483592 | Maintaining stress in a layout design of an integrated circuit having fin-type field-effect transistor devices | Pouya Hashemi, Jeffrey W. Sleight, Tenko Yamashita | 2016-11-01 |
| 9472671 | Method and structure for forming dually strained silicon | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-10-18 |
| 9472555 | Nanosheet CMOS with hybrid orientation | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-10-18 |
| 9472471 | Hybrid orientation vertically stacked III-V and Ge gate-all-around CMOS | Pouya Hashemi, Sanghoon Lee, Alexander Reznicek | 2016-10-18 |
| 9466702 | Semiconductor device including multiple fin heights | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-10-11 |
| 9466690 | Precisely controlling III-V height | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-10-11 |
| 9443982 | Vertical transistor with air gap spacers | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-09-13 |
| 9437427 | Controlled confined lateral III-V epitaxy | Lukas Czornomaz, Pouya Hashemi, Alexander Reznicek | 2016-09-06 |
| 9425293 | Stacked nanowires with multi-threshold voltage solution for pFETs | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-08-23 |
| 9425291 | Stacked nanosheets by aspect ratio trapping | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-08-23 |
| 9406748 | Perfectly shaped controlled nanowires | Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2016-08-02 |
| 9373624 | FinFET devices including epitaxially grown device isolation regions, and a method of manufacturing same | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2016-06-21 |