Issued Patents All Time
Showing 176–200 of 316 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9953973 | Diode connected vertical transistor | Pouya Hashemi, Alexander Reznicek | 2018-04-24 |
| 9953884 | Field effect transistor including strained germanium fins | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-04-24 |
| 9947778 | Lateral bipolar junction transistor with controlled junction | Pouya Hashemi, Tak H. Ning, Alexander Reznicek | 2018-04-17 |
| 9947775 | Replacement III-V or germanium nanowires by unilateral confined epitaxial growth | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-04-17 |
| 9947675 | Mask-programmable ROM using a vertical FET integration process | Pouya Hashemi, Tak H. Ning, Alexander Reznicek | 2018-04-17 |
| 9947649 | Large area electrostatic dischage for vertical transistor structures | Pouya Hashemi, Alexander Reznicek, Jeng-Bang Yau | 2018-04-17 |
| 9941370 | Vertical field-effect-transistors having multiple threshold voltages | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-04-10 |
| 9935185 | Superlattice lateral bipolar junction transistor | Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek | 2018-04-03 |
| 9929270 | Gate all-around FinFET device and a method of manufacturing same | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-03-27 |
| 9929266 | Method and structure for incorporating strain in nanosheet devices | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-03-27 |
| 9922942 | Support for long channel length nanowire transistors | Isaac Lauer, Tenko Yamashita, Jeffrey W. Sleight | 2018-03-20 |
| 9917179 | Stacked nanowire devices formed using lateral aspect ratio trapping | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-03-13 |
| 9917175 | Tapered vertical FET having III-V channel | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-03-13 |
| 9905649 | Tensile strained nFET and compressively strained pFET formed on strain relaxed buffer | Keith E. Fogel, Pouya Hashemi, Alexander Reznicek | 2018-02-27 |
| 9899495 | Vertical transistors with reduced bottom electrode series resistance | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-02-20 |
| 9893151 | Method and apparatus providing improved thermal conductivity of strain relaxed buffer | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-02-13 |
| 9893207 | Programmable read only memory (ROM) integrated in tight pitch vertical transistor structures | Pouya Hashemi, Tak H. Ning, Alexander Reznicek | 2018-02-13 |
| 9887197 | Structure containing first and second vertically stacked nanosheets having different crystallographic orientations | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-02-06 |
| 9876015 | Tight pitch inverter using vertical transistors | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-01-23 |
| 9875896 | Method for forming a strained semiconductor layer including replacing an etchable material formed under the strained semiconductor layer with a dielectric layer | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-01-23 |
| 9871140 | Dual strained nanosheet CMOS and methods for fabricating | Michael A. Guillorn, Pouya Hashemi, Alexander Reznicek | 2018-01-16 |
| 9865462 | Strain relaxed buffer layers with virtually defect free regions | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-01-09 |
| 9859301 | Methods for forming hybrid vertical transistors | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-01-02 |
| 9859420 | Tapered vertical FET having III-V channel | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-01-02 |
| 9859371 | Semiconductor device including a strain relief buffer | Kangguo Cheng, Pouya Hashemi, Alexander Reznicek | 2018-01-02 |