Issued Patents All Time
Showing 526–548 of 548 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9455314 | Y-FET with self-aligned punch-through-stop (PTS) doping | Kangguo Cheng, Ramachandra Divakaruni | 2016-09-27 |
| 9443977 | FinFET with reduced source and drain resistance | Kangguo Cheng, Xin Miao, Junli Wang | 2016-09-13 |
| 9431521 | Stress memorization technique for strain coupling enhancement in bulk finFET device | Kangguo Cheng, Chun-Chen Yeh | 2016-08-30 |
| 9431425 | Directly forming SiGe fins on oxide | Kangguo Cheng, Hong He, Junli Wang | 2016-08-30 |
| 9425196 | Multiple threshold voltage FinFETs | Kangguo Cheng, Ramachandra Divakaruni, Fee Li Lie | 2016-08-23 |
| 9397215 | FinFET with reduced source and drain resistance | Kangguo Cheng, Xin Miao, Junli Wang | 2016-07-19 |
| 9391204 | Asymmetric FET | Kangguo Cheng, Joseph Ervin, Chengwen Pei, Geng Wang | 2016-07-12 |
| 9379110 | Method of fabrication of ETSOI CMOS device by sidewall image transfer (SIT) | Kangguo Cheng | 2016-06-28 |
| 9379221 | Bottom-up metal gate formation on replacement metal gate finFET devices | Hong He, Junli Wang, Chih-Chao Yang | 2016-06-28 |
| 9343320 | Pattern factor dependency alleviation for eDRAM and logic devices with disposable fill to ease deep trench integration with fins | Kangguo Cheng, Joseph Ervin, Chengwen Pei, Geng Wang | 2016-05-17 |
| 9276013 | Integrated formation of Si and SiGe fins | Bruce B. Doris, Hong He, Junli Wang, Chih-Chao Yang | 2016-03-01 |
| 9228994 | Nanochannel electrode devices | Kangguo Cheng, Joseph Ervin, Chengwen Pei, Geng Wang | 2016-01-05 |
| 9219153 | Methods of forming gate structures for FinFET devices and the resulting semiconductor products | Ruilong Xie, Shom Ponoth | 2015-12-22 |
| 9190321 | Self-forming embedded diffusion barriers | Cyril Cabral, Jr., Daniel C. Edelstein, Takeshi Nogami | 2015-11-17 |
| 9159834 | Faceted semiconductor nanowire | Kangguo Cheng, Zhen Zhang, Yu Zhu | 2015-10-13 |
| 9105617 | Methods and structures for eliminating or reducing line end epi material growth on gate structures | Ruilong Xie, Shom Ponoth | 2015-08-11 |
| 9064745 | Sublithographic width finFET employing solid phase epitaxy | Chengwen Pei, Kangguo Cheng, Joseph Ervin, Ravi M. Todi, Geng Wang | 2015-06-23 |
| 9059257 | Self-aligned vias formed using sacrificial metal caps | Chih-Chao Yang, Yunpeng Yin | 2015-06-16 |
| 9059139 | Raised source/drain and gate portion with dielectric spacer or air gap spacer | Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2015-06-16 |
| 9057670 | Transmission electron microscope sample fabrication | James J. Demarest | 2015-06-16 |
| 9053926 | Cyclical physical vapor deposition of dielectric layers | Paul C. Jamison, Vamsi K. Paruchuri, Tuan A. Vo, Takaaki Tsunoda, Sanjay Shinde | 2015-06-09 |
| 9035365 | Raised source/drain and gate portion with dielectric spacer or air gap spacer | Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek | 2015-05-19 |
| 8901711 | Horizontal metal-insulator-metal capacitor | Chih-Chao Yang, Yunpeng Yin | 2014-12-02 |