Issued Patents All Time
Showing 26–50 of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10971504 | Three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple | — | 2021-04-06 |
| 10910312 | Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices | Terence B. Hook | 2021-02-02 |
| 10903165 | Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices | Terence B. Hook | 2021-01-26 |
| 10903307 | Fabrication of a MIM capacitor structure with via etch control with integrated maskless etch tuning layers | Son V. Nguyen | 2021-01-26 |
| 10833081 | Forming isolated contacts in a stacked vertical transport field effect transistor (VTFET) | Chen Zhang, Heng Wu, Tenko Yamashita | 2020-11-10 |
| 10804204 | Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate | Lawrence A. Clevenger, Charles L. Arvin | 2020-10-13 |
| 10770460 | Vertical field-effect transistors for monolithic three-dimensional semiconductor integrated circuit devices | — | 2020-09-08 |
| 10755985 | Gate metal patterning for tight pitch applications | Shogo Mochizuki, Alexander Reznicek, Junli Wang | 2020-08-25 |
| 10748901 | Interlayer via contacts for monolithic three-dimensional semiconductor integrated circuit devices | Nicolas Loubet, Terence B. Hook | 2020-08-18 |
| 10727139 | Three-dimensional monolithic vertical field effect transistor logic gates | Terry Hook, Ardasheir Rahman, Chen Zhang | 2020-07-28 |
| 10714393 | Middle of the line subtractive self-aligned contacts | Balasubramanian Pranatharthiharan | 2020-07-14 |
| 10714420 | High cutoff frequency metal-insulator-metal capacitors implemented using via contact configurations | Joel A. Silberman, Robert A. Groves | 2020-07-14 |
| 10700067 | Vertical field-effect transistors for monolithic three-dimensional semiconductor integrated circuit devices | — | 2020-06-30 |
| 10700209 | Independent gate FinFET with backside gate contact | Terence B. Hook, Tenko Yamashita | 2020-06-30 |
| 10692768 | Vertical transport field-effect transistor architecture | Chen Zhang, Oleg Gluschenkov, Tenko Yamashita | 2020-06-23 |
| 10679890 | Nanosheet structure with isolated gate | Alexander Reznicek, Xin Miao | 2020-06-09 |
| 10636791 | Vertical field-effect transistors for monolithic three-dimensional semiconductor integrated circuit devices | — | 2020-04-28 |
| 10607938 | Power distribution networks for monolithic three-dimensional semiconductor integrated circuit devices | Terence B. Hook | 2020-03-31 |
| 10608080 | Bulk to silicon on insulator device | Terence B. Hook, Tenko Yamashita | 2020-03-31 |
| 10600694 | Gate metal patterning for tight pitch applications | Shogo Mochizuki, Alexander Reznicek, Junli Wang | 2020-03-24 |
| 10593681 | Three-dimensional monolithic vertical transistor memory cell with unified inter-tier cross-couple | — | 2020-03-17 |
| 10580738 | Direct bonded heterogeneous integration packaging structures | Kamal K. Sikka, Jon A. Casey, Arvind Kumar, Dinesh Gupta, Charles L. Arvin +5 more | 2020-03-03 |
| 10573521 | Gate metal patterning to avoid gate stack attack due to excessive wet etching | Junli Wang, Alexander Reznicek, Shogo Mochizuki | 2020-02-25 |
| 10546915 | Buried MIM capacitor structure with landing pads | Alexander Reznicek, Praneet Adusumilli, Oscar van der Straten | 2020-01-28 |
| 10546918 | Multilayer buried metal-insultor-metal capacitor structures | Alexander Reznicek, Oscar van der Straten, Praneet Adusumilli | 2020-01-28 |