Issued Patents All Time
Showing 51–75 of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10535608 | Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate | Lawrence A. Clevenger, Charles L. Arvin | 2020-01-14 |
| 10483344 | Fabrication of a MIM capacitor structure with via etch control with integrated maskless etch tuning layers | Son V. Nguyen | 2019-11-19 |
| 10461148 | Multilayer buried metal-insultor-metal capacitor structures | Alexander Reznicek, Oscar van der Straten, Praneet Adusumilli | 2019-10-29 |
| 10446606 | Back-side memory element with local memory select transistor | Arvind Kumar | 2019-10-15 |
| 10373874 | Middle of the line subtractive self-aligned contacts | Balasubramanian Pranatharthiharan | 2019-08-06 |
| 10332959 | Bulk to silicon on insulator device | Terence B. Hook, Tenko Yamashita | 2019-06-25 |
| 10325821 | Three-dimensional stacked vertical transport field effect transistor logic gate with buried power bus | Terry Hook, Ardasheir Rahman, Chen Zhang | 2019-06-18 |
| 10283411 | Stacked vertical transistor device for three-dimensional monolithic integration | Terence B. Hook | 2019-05-07 |
| 10243043 | Self-aligned air gap spacer for nanosheet CMOS devices | Shogo Mochizuki, Alexander Reznicek, Junli Wang | 2019-03-26 |
| 10229915 | Mirror contact capacitor | Terence B. Hook, Tenko Yamashita | 2019-03-12 |
| 10217674 | Three-dimensional monolithic vertical field effect transistor logic gates | Terry Hook, Ardasheir Rahman, Chen Zhang | 2019-02-26 |
| 10211341 | Tensile strained high percentage silicon germanium alloy FinFETS | Bruce B. Doris, Pouya Hashemi, Alexander Reznicek, Robin M. Schulz | 2019-02-19 |
| 10199352 | Wafer bonding edge protection using double patterning with edge exposure | — | 2019-02-05 |
| 10192888 | Metallized junction FinFET structures | Bruce B. Doris, Pranita Kerber, Alexander Reznicek | 2019-01-29 |
| 10147815 | Fully silicided linerless middle-of-line (MOL) contact | Tenko Yamashita | 2018-12-04 |
| 10128377 | Independent gate FinFET with backside gate contact | Terence B. Hook, Tenko Yamashita | 2018-11-13 |
| 10121877 | Vertical field effect transistor with metallic bottom region | Terence B. Hook, Tenko Yamashita | 2018-11-06 |
| 10103065 | Gate metal patterning for tight pitch applications | Shogo Mochizuki, Alexander Reznicek, Junli Wang | 2018-10-16 |
| 10032674 | Middle of the line subtractive self-aligned contacts | Balasubramanian Pranatharthiharan | 2018-07-24 |
| 9997607 | Mirrored contact CMOS with self-aligned source, drain, and back-gate | Terence B. Hook, Tenko Yamashita | 2018-06-12 |
| 9991339 | Bulk to silicon on insulator device | Terence B. Hook, Tenko Yamashita | 2018-06-05 |
| 9978871 | Bulk to silicon on insulator device | Terence B. Hook, Tenko Yamashita | 2018-05-22 |
| 9954058 | Self-aligned air gap spacer for nanosheet CMOS devices | Shogo Mochizuki, Alexander Reznicek, Junli Wang | 2018-04-24 |
| 9881925 | Mirror contact capacitor | Terence B. Hook, Tenko Yamashita | 2018-01-30 |
| 9853151 | Fully silicided linerless middle-of-line (MOL) contact | Tenko Yamashita | 2017-12-26 |