Issued Patents All Time
Showing 51–75 of 98 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7668037 | Storage array including a local clock buffer with programmable timing | Gary Dale Carpenter, Fadi H. Gebara, Jerry Chang Jui Kao, Kevin John Nowka, Liang Pang | 2010-02-23 |
| 7620510 | Pulsed ring oscillator circuit for storage cell read timing evaluation | Gary Dale Carpenter, Kevin John Nowka, Liang Pang | 2009-11-17 |
| 7564739 | Storage cell design evaluation circuit including a wordline timing and cell access detection circuit | Sebastian Ehrenreich, Chun-Tao Li, Hung Kai Ngo | 2009-07-21 |
| 7551508 | Energy efficient storage device using per-element selectable power supply voltages | Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif, Hung C. Ngo | 2009-06-23 |
| 7545690 | Method for evaluating memory cell performance | Jerry Chang Jui Kao, Hung C. Ngo, Kevin John Nowka | 2009-06-09 |
| 7487374 | Dynamic power and clock-gating method and circuitry with sleep mode based on estimated time for receipt of next wake-up signal | Ying Liu, Hung C. Ngo | 2009-02-03 |
| 7459950 | Pulsed local clock buffer (LCB) characterization ring oscillator | Hung C. Ngo, James D. Warnock, Dieter Wendel | 2008-12-02 |
| 7414904 | Method for evaluating storage cell design using a wordline timing and cell access detection circuit | Sebastian Ehrenreich, Chun-Tao Li, Hung C. Ngo | 2008-08-19 |
| 7408829 | Methods and arrangements for enhancing power management systems in integrated circuits | Hung C. Ngo | 2008-08-05 |
| 7409305 | Pulsed ring oscillator circuit for storage cell read timing evaluation | Gary Dale Carpenter, Kevin John Nowka, Liang Pang | 2008-08-05 |
| 7405982 | Methods to improve the operation of SOI devices | Roy C. Flaker, Louis L. Hsu | 2008-07-29 |
| 7372305 | Scannable dynamic logic latch circuit | Hung C. Ngo, James D. Warnock, Dieter Wendel | 2008-05-13 |
| 7349271 | Cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance | Jerry Chang Jui Kao, Hung C. Ngo, Kevin John Nowka | 2008-03-25 |
| 7336105 | Dual gate transistor keeper dynamic logic | Ching-Te Chuang, Keunwoo Kim, Kevin John Nowka | 2008-02-26 |
| 7323908 | Cascaded pass-gate test circuit with interposed split-output drive devices | Ching-Te Chuang, Hung C. Ngo | 2008-01-29 |
| 7298176 | Dual-gate dynamic logic circuit with pre-charge keeper | Hung C. Ngo, Ching-Te Chuang, Keunwoo Kim, Kevin John Nowka | 2007-11-20 |
| 7288975 | Method and apparatus for fail-safe and restartable system clock generation | Hung C. Ngo, Gary Dale Carpenter, Fadi H. Gebara | 2007-10-30 |
| 7276932 | Power-gating cell for virtual power rail control | Jethro C. Law, Hung C. Ngo, Kevin John Nowka | 2007-10-02 |
| 7266707 | Dynamic leakage control circuit | Hung C. Ngo, Kevin John Nowka, Rajiv V. Joshi | 2007-09-04 |
| 7265589 | Independent gate control logic circuitry | Ching-Te Chuang, Keunwoo Kim, Kevin John Nowka | 2007-09-04 |
| 7219244 | Control circuitry for power gating virtual power supply rails at differing voltage potentials | Hung C. Ngo, Kevin John Nowka | 2007-05-15 |
| 7216141 | Computing carry-in bit to most significant bit carry save adder in current stage | Wendy A. Belluomini, Ramyanshu Datta, Chandler McDowell, Robert K. Montoye, Hung C. Ngo | 2007-05-08 |
| 7202705 | Dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control | Hung C. Ngo, Harmander Singh Deogun, AJ KleinOsowski | 2007-04-10 |
| 7193446 | Dynamic logic circuit incorporating reduced leakage state-retaining devices | Hung C. Ngo, Harmander Singh Deogun, AJ KleinOsowski | 2007-03-20 |
| 7142015 | Fast turn-off circuit for controlling leakage | Hung C. Ngo, Kevin John Nowka | 2006-11-28 |