Issued Patents All Time
Showing 26–50 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10353827 | Zone-SDID mapping scheme for TLB purges | Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi +2 more | 2019-07-16 |
| 10353828 | Zone-SDID mapping scheme for TLB purges | Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi +2 more | 2019-07-16 |
| 10353825 | Suspending translation look-aside buffer purge execution in a multi-processor environment | Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Kohler +2 more | 2019-07-16 |
| 10289562 | Incorporating purge history into least-recently-used states of a translation lookaside buffer | Uwe Brandt, Markus Helms, Thomas Kohler | 2019-05-14 |
| 10248575 | Suspending translation look-aside buffer purge execution in a multi-processor environment | Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Thomas Kohler +2 more | 2019-04-02 |
| 10176002 | Quiesce handling in multithreaded environments | Michael Fee, Ute Gaertner, Lisa C. Heller, Thomas Koehler, Jennifer A. Navarro | 2019-01-08 |
| 10140217 | Link consistency in a hierarchical TLB with concurrent table walks | Uwe Brandt, Thomas Koehler, Markus Helms, Martin Recktenwald | 2018-11-27 |
| 10127159 | Link consistency in a hierarchical TLB with concurrent table walks | Uwe Brandt, Thomas Koehler, Markus Helms, Martin Recktenwald | 2018-11-13 |
| 10083124 | Translating virtual memory addresses to physical addresses | Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler | 2018-09-25 |
| 10025608 | Quiesce handling in multithreaded environments | Michael Fee, Ute Gaertner, Lisa C. Heller, Thomas Koehler, Jennifer A. Navarro | 2018-07-17 |
| 9845965 | Automated functional diagnosis | Peter Schmidlin | 2017-12-19 |
| 9760511 | Efficient interruption routing for a multithreaded processor | Jonathan D. Bradbury, Fadi Y. Busaba, Mark S. Farrell, Charles W. Gainey, Jr., Dan F. Greiner +7 more | 2017-09-12 |
| 9715458 | Multiprocessor computer system | Thomas Koehler | 2017-07-25 |
| 9678830 | Recovery improvement for quiesced systems | Michael Fee, Ute Gaertner, Lisa C. Heller, Jennifer A. Navarro, Rebecca S. Wisniewski | 2017-06-13 |
| 9665424 | Recovery improvement for quiesced systems | Michael Fee, Ute Gaertner, Lisa C. Heller, Jennifer A. Navarro, Rebecca S. Wisniewski | 2017-05-30 |
| 9658852 | Updating of shadow registers in N:1 clock domain | Thomas Koehler | 2017-05-23 |
| 9311137 | Delaying interrupts for a transactional-execution facility | Guenter Gerwig, Christian Jacobi | 2016-04-12 |
| 9207706 | Generating monotonically increasing TOD values in a multiprocessor system | Guenter Gerwig, Christian Jacobi, Chung-Lung K. Shum, Timothy J. Slegel | 2015-12-08 |
| 8683261 | Out of order millicode control operation | Michael Cremer, Guenter Gerwig, Peter Probst | 2014-03-25 |
| 8516336 | Latch arrangement for an electronic digital system, method, data processing program, and computer program product for implementing a latch arrangement | Michael Cremer, Guenter Gerwig | 2013-08-20 |
| 8095821 | Debugging for multiple errors in a microprocessor environment | Ulrich Mayer, Timothy J. Slegel, Chung-Lung K. Shum, Guenter Gerwig | 2012-01-10 |
| 8061684 | Anti-twist device for an actuating motor | Urs NIEDERHAUSER | 2011-11-22 |
| 7931525 | Air flow control in a ventilating pipe | — | 2011-04-26 |
| 7667476 | Measuring module for rapid measurement of electrical, electronic and mechanical components at cryogenic temperatures and measuring device having such a module | Olivier Zogmal, Daniel Guy Baumann | 2010-02-23 |
| 7650535 | Array delete mechanisms for shipping a microprocessor with defective arrays | Norbert Hagspiel, William V. Huott, Brian R. Prasky, Richard F. Rizzolo, Rolf Sautter | 2010-01-19 |