Issued Patents All Time
Showing 401–425 of 496 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9196591 | Chip with shelf life | — | 2015-11-24 |
| 9196485 | Stacked sidewall patterning | — | 2015-11-24 |
| 9129863 | Method to form dual channel group III-V and Si/Ge FINFET CMOS | Daniele Caimi, Lukas Czornomaz, Jean Fompeyrine | 2015-09-08 |
| 9123654 | Trilayer SIT process with transfer layer for FINFET patterning | — | 2015-09-01 |
| 9123585 | Method to form group III-V and Si/Ge FINFET on insulator | Lukas Czornomaz, Jean Fompeyrine | 2015-09-01 |
| 9112031 | Reduced resistance finFET device with late spacer self aligned contact | — | 2015-08-18 |
| 9099412 | Selective laser anneal on semiconductor material | — | 2015-08-04 |
| 9093532 | Overlapped III-V finFET with doped semiconductor extensions | Cheng-Wei Cheng, Kuen-Ting Shiu, Yanning Sun | 2015-07-28 |
| 9087772 | Device and method for forming sharp extension region with controllable junction depth and lateral overlap | Isaac Lauer, Ghavam G. Shahidi | 2015-07-21 |
| 9064885 | Electrostatic discharge resistant diodes | Huiming Bu, Robert J. Gauthier, Jr., Terence B. Hook, Tenko Yamashita | 2015-06-23 |
| 9059043 | Fin field effect transistor with self-aligned source/drain regions | Tenko Yamashita | 2015-06-16 |
| 9059288 | Overlapped III-V finfet with doped semiconductor extensions | Cheng-Wei Cheng, Kuen-Ting Shiu, Yanning Sun | 2015-06-16 |
| 9059031 | DRAM with dual level word lines | Babar A. Khan | 2015-06-16 |
| 9054192 | Integration of Ge-containing fins and compound semiconductor fins | Kevin K. Chan, Cheng-Wei Cheng, Young-Hee Kim, Masaharu Kobayashi, Dae-Gyu Park +1 more | 2015-06-09 |
| 9054124 | Electrostatic discharge resistant diodes | Huiming Bu, Robert J. Gauthier, Jr., Terence B. Hook, Tenko Yamashita | 2015-06-09 |
| 9048318 | Dual material finFET on same substrate | — | 2015-06-02 |
| 9041151 | Fin eFuse formed by trench silicide process | Christian Lavoie, Dan Moy | 2015-05-26 |
| 9034748 | Process variability tolerant hard mask for replacement metal gate finFET devices | Christopher V. Baiocco, Kevin K. Chan, Young-Hee Kim, Masaharu Kobayashi, Fei Liu +4 more | 2015-05-19 |
| 9018686 | Dual gate finFET devices | Veeraraghavan S. Basker, Tenko Yamashita | 2015-04-28 |
| 9000413 | Overlap capacitance nanowire | — | 2015-04-07 |
| 8994081 | Stacked semiconductor nanowires with tunnel spacers | — | 2015-03-31 |
| 8987800 | Semiconductor structures with deep trench capacitor and methods of manufacture | Kevin K. Chan, Sivananda K. Kanakasabapathy, Babar A. Khan, Masaharu Kobayashi, Theodorus E. Standaert +1 more | 2015-03-24 |
| 8969152 | Field-effect transistor (FET) with source-drain contact over gate spacer | Kevin K. Chan, Wilfried E. Haensch, Min Yang | 2015-03-03 |
| 8969149 | Stacked semiconductor nanowires with tunnel spacers | — | 2015-03-03 |
| 8969963 | Vertical source/drain junctions for a finFET including a plurality of fins | Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh | 2015-03-03 |