Issued Patents All Time
Showing 351–375 of 496 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9484250 | Air gap contact formation for reducing parasitic capacitance | — | 2016-11-01 |
| 9478708 | Embedded gallium—nitride in silicon | William J. Gallagher, Devendra K. Sadana, Ghavam G. Shahidi | 2016-10-25 |
| 9478534 | Lateral BiCMOS replacement metal gate | Jin Cai, Tak H. Ning | 2016-10-25 |
| 9472651 | Spacerless fin device with reduced parasitic resistance and capacitance and method to fabricate same | — | 2016-10-18 |
| 9472654 | Forming low parasitic trim gate last MOSFET | — | 2016-10-18 |
| 9455347 | Mandrel removal last in lateral semiconductor growth and structure for same | — | 2016-09-27 |
| 9450381 | Monolithic integrated photonics with lateral bipolar and BiCMOS | Jin Cai, Ning Li, Tak H. Ning, Jean-Olivier Plouchart, Devendra K. Sadana | 2016-09-20 |
| 9437614 | Dual-semiconductor complementary metal-oxide-semiconductor device | Sanghoon Lee, Renee T. Mo, Yanning Sun | 2016-09-06 |
| 9431352 | Chip with shelf life | — | 2016-08-30 |
| 9423563 | Variable buried oxide thickness for a waveguide | Russell A. Budd, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana | 2016-08-23 |
| 9418846 | Selective dopant junction for a group III-V semiconductor device | Kevin K. Chan, Marinus Hopstaken, Young-Hee Kim, Masaharu Kobayashi, Deborah A. Neumayer +3 more | 2016-08-16 |
| 9419091 | Trenched gate with sidewall airgap spacer | — | 2016-08-16 |
| 9419102 | Method to reduce parasitic gate capacitance and structure for same | — | 2016-08-16 |
| 9412840 | Sacrificial layer for replacement metal semiconductor alloy contact formation | Tenko Yamashita | 2016-08-09 |
| 9412664 | Dual material finFET on single substrate | — | 2016-08-09 |
| 9401583 | Laser structure on silicon using aspect ratio trapping growth | Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu | 2016-07-26 |
| 9395490 | Variable buried oxide thickness for a waveguide | Russell A. Budd, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana | 2016-07-19 |
| 9397005 | Dual-material mandrel for epitaxial crystal growth on silicon | Sanghoon Lee, Brent A. Wacaser | 2016-07-19 |
| 9397161 | Reduced current leakage semiconductor device | Cheng-Wei Cheng, Pranita Kerber, Young-Hee Kim, Yanning Sun | 2016-07-19 |
| 9391074 | Structure for FinFET fins | Tenko Yamashita | 2016-07-12 |
| 9373550 | Selectively degrading current resistance of field effect transistor devices | Veeraraghavan S. Basker, Dieter Wendel, Tenko Yamashita | 2016-06-21 |
| 9372307 | Monolithically integrated III-V optoelectronics with SI CMOS | Russell A. Budd, Ning Li, Jean-Olivier Plouchart, Devendra K. Sadana | 2016-06-21 |
| 9368569 | Punch through stopper for semiconductor device | Tenko Yamashita | 2016-06-14 |
| 9362444 | Optoelectronics and CMOS integration on GOI substrate | Ning Li, Devendra K. Sadana | 2016-06-07 |
| 9362281 | Group III nitride integration with CMOS technology | Can Bayram, Christopher P. D'Emic, William J. Gallagher, Devendra K. Sadana | 2016-06-07 |