Issued Patents All Time
Showing 276–300 of 408 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6869895 | Method for adjusting capacitance of an on-chip capacitor | Lawrence A. Clevenger, Timothy J. Dalton, Louis L. Hsu, Keith Kwong Hon Wong, Chih-Chao Yang | 2005-03-22 |
| 6869846 | Forming electronic structures having dual dielectric thicknesses and the structure so formed | Louis L. Hsu, Jack A. Mandelman, Richard Strub, William R. Tonti | 2005-03-22 |
| 6864540 | High performance FET with elevated source/drain region | Rama Divakaruni, Louis C. Hsu, Rajiv V. Joshi | 2005-03-08 |
| 6841826 | Low-GIDL MOSFET structure and method for fabrication | Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov, Jack A. Mandelman | 2005-01-11 |
| 6808981 | Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI | Jack A. Mandelman, Ramachandra Divakaruni, Gary B. Bronner | 2004-10-26 |
| 6806534 | Damascene method for improved MOS transistor | Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov, Jack A. Mandelman | 2004-10-19 |
| 6794721 | Integration system via metal oxide conversion | Lawrence A. Clevenger, Louis L. Hsu, Joseph F. Shepard, Jr. | 2004-09-21 |
| 6794726 | MOS antifuse with low post-program resistance | William R. Tonti | 2004-09-21 |
| 6780694 | MOS transistor | Bruce B. Doris, Omer H. Dokumaci, Jack A. Mandelman | 2004-08-24 |
| 6777733 | Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays | Jack A. Mandelman, Ramachandra Divakaruni | 2004-08-17 |
| 6768063 | Structure and method for shadow mask electrode | Lawrence A. Clevenger, Louis L. Hsu, Li-Kong Wang, Kwong Hon Wong | 2004-07-27 |
| 6762447 | Field-shield-trench isolation for gigabit DRAMs | Jack A. Mandelman, Rama Divakaruni, Giuseppe Larosa, Ulrike Gruening | 2004-07-13 |
| 6759702 | Memory cell with vertical transistor and trench capacitor with reduced burried strap | Ramachandra Divakaruni, Jack A. Mandelman | 2004-07-06 |
| 6743670 | High dielectric constant materials forming components of DRAM such as deep-trench capacitors and gate dielectric (insulators) for support circuits | Lawrence A. Clevenger, Louis L. Hsu, Joseph F. Shepard, Jr. | 2004-06-01 |
| 6730552 | MOSFET with decoupled halo before extension | Wagdi W. Abadeer, Jeffrey S. Brown, Kiran V. Chatty, Robert J. Gauthier, Jr., William R. Tonti | 2004-05-04 |
| 6727539 | Embedded vertical DRAM arrays with silicided bitline and polysilicon interconnect | Ramachandra Divakaruni, Ulrike Gruening, Jack A. Mandelman, Larry Nesbit | 2004-04-27 |
| 6727540 | Structure and method of fabricating embedded DRAM having a vertical device array and a bordered bitline contact | Ramachandra Divakaruni, Babar A. Khan | 2004-04-27 |
| 6724029 | Twin-cell flash memory structure and method | Louis L. Hsu, Chung H. Lam, Jack A. Mandelman, William R. Tonti | 2004-04-20 |
| 6724031 | Method for preventing strap-to-strap punch through in vertical DRAMs | Hiroyuki Akatsu, Dureseti Chidambarrao, Ramachandra Divakaruni, Jack A. Mandelman | 2004-04-20 |
| 6720630 | Structure and method for MOSFET with metallic gate electrode | Jack A. Mandelman, Oleg Gluschenkov | 2004-04-13 |
| 6720595 | Three-dimensional island pixel photo-sensor | Lawrence A. Clevenger, Louis L. Hsu, Li-Kong Wang, Kwong Hon Wong | 2004-04-13 |
| 6707095 | Structure and method for improved vertical MOSFET DRAM cell-to-cell isolation | Dureseti Chidambarrao, Jack A. Mandelman | 2004-03-16 |
| 6700161 | Variable resistor structure and method for forming and programming a variable resistor for electronic circuits | Louis L. Hsu, Chandrasekhar Narayan | 2004-03-02 |
| 6693041 | Self-aligned STI for narrow trenches | Ramachandra Divakaruni, Jack A. Mandelman | 2004-02-17 |
| 6686637 | Gate structure with independently tailored vertical doping profile | Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov, Jack A. Mandelman | 2004-02-03 |