Issued Patents All Time
Showing 51–75 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8673738 | Shallow trench isolation structures | Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Pranita Kulkarni, Arvind Kumar +1 more | 2014-03-18 |
| 8673708 | Replacement gate ETSOI with sharp junction | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz | 2014-03-18 |
| 8664050 | Structure and method to improve ETSOI MOSFETS with back gate | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni | 2014-03-04 |
| 8642415 | Semiconductor substrate with transistors having different threshold voltages | Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Pranita Kulkarni, Alexander Reznicek | 2014-02-04 |
| 8633085 | Dual-depth self-aligned isolation structure for a back gate electrode | Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi | 2014-01-21 |
| 8629008 | Electrical isolation structures for ultra-thin semiconductor-on-insulator devices | David V. Horak, Charles W. Koburger, III, Shom Ponoth | 2014-01-14 |
| 8629007 | Method of improving replacement metal gate fill | James J. Demarest | 2014-01-14 |
| 8623712 | Bulk fin-field effect transistors with well defined isolation | Kangguo Cheng, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2014-01-07 |
| 8623730 | Method for fabricating silicon-on-insulator transistor with self-aligned borderless source/drain contacts | Susan S. Fan, David V. Horak, Charles W. Koburger, III | 2014-01-07 |
| 8617961 | Post-gate isolation area formation for fin field effect transistor device | Sanjay C. Mehta, Theodorus E. Standaert | 2013-12-31 |
| 8614486 | Low resistance source and drain extensions for ETSOI | Hemanth Jagannathan, Sivananda K. Kanakasabapathy, Sanjay C. Mehta | 2013-12-24 |
| 8604539 | Bulk fin-field effect transistors with well defined isolation | Kangguo Cheng, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2013-12-10 |
| 8598663 | Semiconductor structure having NFET and PFET formed in SOI substrate with underlapped extensions | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi | 2013-12-03 |
| 8592290 | Cut-very-last dual-EPI flow | Veeraraghavan S. Basker, Huiming Bu, Kangguo Cheng, Nicolas Loubet, Shom Ponoth +3 more | 2013-11-26 |
| 8592263 | FinFET diode with increased junction area | Theodorus E. Standaert, Kangguo Cheng, Shom Ponoth, Tenko Yamashita | 2013-11-26 |
| 8581320 | MOS capacitors with a finfet process | Kangguo Cheng, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2013-11-12 |
| 8569152 | Cut-very-last dual-epi flow | Veeraraghavan S. Basker, Huiming Bu, Kangguo Cheng, Nicolas Loubet, Shom Ponoth +3 more | 2013-10-29 |
| 8569125 | FinFET with improved gate planarity | Theodorus E. Standaert, Kangguo Cheng, Shom Ponoth, Soon-Cheon Seo, Tenko Yamashita | 2013-10-29 |
| 8551872 | Low series resistance transistor structure on silicon on insulator layer | Kangguo Chen, Bruce B. Doris, Amlan Majumdar, Sanjay C. Mehta | 2013-10-08 |
| 8486778 | Low resistance source and drain extensions for ETSOI | Hemanth Jagannathan, Sivananda K. Kanakasabapathy, Sanjay C. Mehta | 2013-07-16 |
| 8455932 | Local interconnect structure self-aligned to gate structure | Ali Khakifirooz, Kangguo Cheng, Bruce B. Doris, Wilfried E. Haensch, Pranita Kulkarni | 2013-06-04 |
| 8440552 | Method to form low series resistance transistor devices on silicon on insulator layer | Kangguo Chen, Bruce B. Doris, Amlan Majumdar, Sanjay C. Mehta | 2013-05-14 |
| 8435846 | Semiconductor devices with raised extensions | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni | 2013-05-07 |
| 8432002 | Method and structure for low resistive source and drain regions in a replacement metal gate process flow | Kangguo Cheng, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2013-04-30 |
| 8420459 | Bulk fin-field effect transistors with well defined isolation | Kangguo Cheng, Shom Ponoth, Theodorus E. Standaert, Tenko Yamashita | 2013-04-16 |