Issued Patents All Time
Showing 76–84 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8399957 | Dual-depth self-aligned isolation structure for a back gate electrode | Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi | 2013-03-19 |
| 8394710 | Semiconductor devices fabricated by doped material layer as dopant source | Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi | 2013-03-12 |
| 8383490 | Borderless contact for ultra-thin body devices | Su Chen Fan, David V. Horak | 2013-02-26 |
| 8377795 | Cut first methodology for double exposure double etch integration | Sivananda K. Kanakasabapathy, Veeraraghavan S. Basker | 2013-02-19 |
| 8372705 | Fabrication of CMOS transistors having differentially stressed spacers | Lahir Shaik Adam, Sanjay C. Mehta, Bruce B. Doris | 2013-02-12 |
| 8358012 | Metal semiconductor alloy structure for low contact resistance | Sivananda K. Kanakasabapathy | 2013-01-22 |
| 8309447 | Method for integrating multiple threshold voltage devices for CMOS | Kangguo Cheng, Bruce B. Doris, Lisa F. Edge, Hemanth Jagannathan, Ali Khakifirooz +1 more | 2012-11-13 |
| 8232179 | Method to improve wet etch budget in FEOL integration | Jason E. Cummings, Lisa F. Edge, David V. Horak, Hemanth Jagannathan, Sanjay C. Mehta | 2012-07-31 |
| 8232607 | Borderless contact for replacement gate employing selective deposition | Lisa F. Edge | 2012-07-31 |