Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7421689 | Processor-architecture for facilitating a virtual machine monitor | Jonathan Ross, Donald Soltis, Rohit Bhatia, Eric Delano | 2008-09-02 |
| 7340630 | Multiprocessor system with interactive synchronization of local clocks | Jonathan Ross | 2008-03-04 |
| 7325228 | Data speculation across a procedure call using an advanced load address table | Jonathan Ross, Achmed R. Zahir | 2008-01-29 |
| 7281116 | Multiprocessor system having plural memory locations for respectively storing TLB-shootdown data for plural processor nodes | Jonathan Ross | 2007-10-09 |
| 7274825 | Image matching using pixel-depth reduction before image comparison | Ruby B. Lee | 2007-09-25 |
| 7155471 | Method and system for determining the correct rounding of a function | Peter Markstein, James M. Hull | 2006-12-26 |
| 7143270 | System and method for adding an instruction to an instruction set architecture | Kevin Rudd, Allan D. Knies, James M. Hull | 2006-11-28 |
| 7103756 | Data processor with individually writable register subword locations | — | 2006-09-05 |
| 7103880 | Floating-point data speculation across a procedure call using an advanced load address table | Jerome C. Huck | 2006-09-05 |
| 7085989 | Optimized testing of bit fields | Sverre Jarp | 2006-08-01 |
| 7080242 | Instruction set reconciliation for heterogeneous symmetric-multiprocessor systems | — | 2006-07-18 |
| 6986131 | Method and apparatus for efficient code generation for modulo scheduled uncounted loops | Carol L. Thompson, Uma Srinivasan, Richard E. Hank | 2006-01-10 |
| 6931515 | Method and system for using dynamic, deferred operation information to control eager deferral of control-speculative loads | Jonathan Ross | 2005-08-16 |
| 6813627 | Method and apparatus for performing integer multiply operations using primitive multi-media operations that operate on smaller operands | James M. Hull | 2004-11-02 |
| 6799263 | Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted | James Callister, Stephen R. Undy | 2004-09-28 |
| 6631460 | Advanced load address table entry invalidation based on register address wraparound | William R. Bry, Alan H. Karp, William Y. Chen | 2003-10-07 |
| 6611910 | Method for processing branch operations | Harshvardhan Sharangpani, Tse-Yu Yeh, Michael Corwin, Millind Mittal, Kent Fielden +3 more | 2003-08-26 |
| 6550001 | Method and implementation of statistical detection of read after write and write after write hazards | Michael Corwin | 2003-04-15 |
| 6505296 | Emulated branch effected by trampoline mechanism | Jonathan Ross, James O. Hays, Jerome C. Huck | 2003-01-07 |
| 6438682 | Method and apparatus for predicting loop exit branches | Mircea Poplingher, Tse-Yu Yeh, Michael Corwin, Wenliang Chen | 2002-08-20 |
| 6308261 | Computer system having an instruction for probing memory latency | Douglas Benson Hunt | 2001-10-23 |
| 6286095 | Computer apparatus having special instructions to force ordered load and store operations | Barry J. Flahive, Michael L. Ziegler, Jerome C. Huck, Stephen G. Burger, Ruby B. Lee +2 more | 2001-09-04 |
| 6237077 | Instruction template for efficient processing clustered branch instructions | Harshvardhan Sharangpani, Michael Corwin, Kent Fielden, Tse-Yu Yeh, Hans Mulder +1 more | 2001-05-22 |
| 6079012 | Computer that selectively forces ordered execution of store and load operations between a CPU and a shared memory | Bernard L. Stumpf, Barry J. Flahive, Jeffrey D. Kurtze, Stephen G. Burger, Ruby B. Lee +1 more | 2000-06-20 |
| 5928356 | Method and apparatus for selectively controlling groups of registers | Roger Golliver, Jerome C. Huck | 1999-07-27 |