Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12394837 | Immersion cooling system including metal-encased, pouch-type battery cells for hot gas flow separation in battery systems of electric vehicles | Taeyoung Han, Chih-hung Yen, Ryan P. Hickey, Matthew Swift, Goro Tamai +1 more | 2025-08-19 |
| 12322779 | Stacked separator plates with coolant flow distribution channels for liquid immersion cooling in battery assemblies | Chih-hung Yen, Stephane Watts, Frederic Albergucci | 2025-06-03 |
| 12148946 | Immersion cooling system for battery systems of electric vehicles | Taeyoung Han, Ryan P. Hickey, Matthew Swift, Chih-hung Yen, Goro Tamai +1 more | 2024-11-19 |
| 11870089 | Battery cell pack | Andrew C. Bobel, Anil K. Sachdev, Patrick H. Clark, Pooja Suresh, Ran Wu +5 more | 2024-01-09 |
| 10289394 | Selective generation of multiple versions of machine code for source code functions for execution on different processor versions and/or architectures | Alfred Huang | 2019-05-14 |
| 9766911 | Support for a non-native application | Abhinav Das, Jiwei Lu, Chandramouli Banerjee | 2017-09-19 |
| 9146831 | Sampling based runtime optimizer for efficient debugging of applications | Jiwei Lu | 2015-09-29 |
| 8627302 | Sampling based runtime optimizer for efficient debugging of applications | Jiwei Lu | 2014-01-07 |
| 8521760 | Dynamic translator for requests for system resources | Abhinav Das, Jiwei Lu, Chandramouli Banerjee | 2013-08-27 |
| 8473930 | Handling signals and exceptions in a dynamic translation environment | Abhinav Das, Jiwei Lu, Chandramouli Banerjee | 2013-06-25 |
| 8346531 | Handling mutex locks in a dynamic binary translation across heterogeneous computer systems | Abhinav Das, Jiwei Lu, Chandramouli Banerjee | 2013-01-01 |
| 8230402 | Testing and debugging of dynamic binary translation | Jiwei Lu, Geetha Vallabhaneni | 2012-07-24 |
| 8090916 | In-circuit programming architecture with processor and delegable flash controller | Jeon-Yung Ray | 2012-01-03 |
| 8020155 | Mechanism for optimizing function execution | Jiwei Lu | 2011-09-13 |
| 7406559 | In-circuit programming architecture with processor, delegable flash controller, and code generator | Albert Sun, Jeon-Yung Ray | 2008-07-29 |
| 6732356 | System and method of using partially resolved predicates for elimination of comparison instruction | — | 2004-05-04 |
| 6637026 | Instruction reducing predicate copy | — | 2003-10-21 |
| 6631465 | Method and apparatus for instruction re-alignment using a branch on a falsehood of a qualifying predicate | Dong Chen | 2003-10-07 |
| 6631460 | Advanced load address table entry invalidation based on register address wraparound | Dale Morris, William R. Bry, Alan H. Karp | 2003-10-07 |
| 6505345 | Optimization of initialization of parallel compare predicates in a computer system | Dong Chen | 2003-01-07 |
| 6351849 | Compiler optimization through combining of memory operations | — | 2002-02-26 |
| 5903749 | Method and apparatus for implementing check instructions that allow for the reuse of memory conflict information if no memory conflict occurs | H. Roland Kenner, Alan H. Karp | 1999-05-11 |
| 5694577 | Memory conflict buffer for achieving memory disambiguation in compile-time code schedule | Tokuzo Kiyohara, Wen-Mei Hwu | 1997-12-02 |