Issued Patents All Time
Showing 76–100 of 175 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9536877 | Methods of forming different spacer structures on integrated circuit products having differing gate pitch dimensions and the resulting products | Ruilong Xie, Kangguo Cheng, Ali Khakifirooz | 2017-01-03 |
| 9536981 | Field effect transistor device spacers | Sanjay C. Mehta, Tenko Yamashita | 2017-01-03 |
| 9530775 | Methods of forming different FinFET devices having different fin heights and an integrated circuit product containing such devices | Ruilong Xie, Kangguo Cheng, Ali Khakifirooz | 2016-12-27 |
| 9515180 | Vertical slit transistor with optimized AC performance | Qing Liu, Chun-Chen Yeh, Ruilong Xie | 2016-12-06 |
| 9502518 | Multi-channel gate-all-around FET | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2016-11-22 |
| 9496354 | Semiconductor devices with dummy gate structures partially on isolation regions | Ruilong Xie, Ajey Poovannummoottil Jacob, Andreas Knorr, Christopher M. Prindle | 2016-11-15 |
| 9496185 | Dual channel finFET with relaxed pFET region | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2016-11-15 |
| 9478634 | Methods of forming replacement gate structures on finFET devices and the resulting devices | Ruilong Xie | 2016-10-25 |
| 9472446 | Methods of forming a FinFET semiconductor device with a unique gate configuration, and the resulting FinFET device | Ruilong Xie, Kangguo Cheng, Ali Khakifirooz | 2016-10-18 |
| 9466722 | Large area contacts for small transistors | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2016-10-11 |
| 9460969 | Macro to monitor n-p bump | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2016-10-04 |
| 9455331 | Method and structure of forming controllable unmerged epitaxial material | Kangguo Cheng, Ali Khakifirooz, Ruilong Xie, Tenko Yamashita | 2016-09-27 |
| 9455330 | Recessing RMG metal gate stack for forming self-aligned contact | Kangguo Cheng, Ali Khakifirooz, Ruilong Xie | 2016-09-27 |
| 9437711 | Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices | Xunyuan Zhang | 2016-09-06 |
| 9431540 | Method for making a semiconductor device with sidewall spacers for confining epitaxial growth | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2016-08-30 |
| 9431539 | Dual-strained nanowire and FinFET devices with dielectric isolation | Yi Qi, Catherine B. Labelle | 2016-08-30 |
| 9425319 | Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same | Ruilong Xie, Ali Khakifirooz, Kangguo Cheng | 2016-08-23 |
| 9425280 | Semiconductor device with low-K spacers | Ruilong Xie, Xunyuan Zhang | 2016-08-23 |
| 9425292 | Field effect transistor device spacers | Sanjay C. Mehta, Tenko Yamashita | 2016-08-23 |
| 9419137 | Stress memorization film and oxide isolation in fins | Abner Bello, Hugh Porter, Daniel T. Pham | 2016-08-16 |
| 9412740 | Integrated circuit product with a gate height registration structure | Ruilong Xie, Michael Wedlake, Ali Khakifirooz, Kangguo Cheng | 2016-08-09 |
| 9412822 | Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device | Ruilong Xie, Kangguo Cheng, Ali Khakifirooz, Ajey Poovannummoottil Jacob, Witold P. Maszara | 2016-08-09 |
| 9406751 | Method for making strained semiconductor device and related methods | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2016-08-02 |
| 9390939 | Methods of forming MIS contact structures for semiconductor devices and the resulting devices | Ruilong Xie, Kangguo Cheng, Ali Khakifirooz | 2016-07-12 |
| 9391200 | FinFETs having strained channels, and methods of fabricating finFETs having strained channels | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2016-07-12 |