Issued Patents All Time
Showing 26–50 of 175 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10355020 | FinFETs having strained channels, and methods of fabricating finFETs having strained channels | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2019-07-16 |
| 10290636 | Semiconductor device having fins with in-situ doped, punch-through stopper layer and related methods | Qing Liu, Chun-Chen Yeh, Ruilong Xie | 2019-05-14 |
| 10276573 | FinFET including tunable fin height and tunable fin width ratio | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2019-04-30 |
| 10256304 | High doped III-V source/drain junctions for field effect transistors | Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh | 2019-04-09 |
| 10249726 | Methods of forming a protection layer on a semiconductor device and the resulting device | Ruilong Xie, Chanro Park | 2019-04-02 |
| 10217869 | Semiconductor structure including low-K spacer material | Kangguo Cheng, Ali Khakifirooz, Ruilong Xie | 2019-02-26 |
| 10153371 | Semiconductor device with fins including sidewall recesses | Qing Liu, Ruilong Xie | 2018-12-11 |
| 10134903 | Vertical slit transistor with optimized AC performance | Qing Liu, Chun-Chen Yeh, Ruilong Xie | 2018-11-20 |
| 10134840 | Series resistance reduction in vertically stacked silicon nanowire transistors | Chun-Chen Yeh, Qing Liu, Ruilong Xie | 2018-11-20 |
| 10062762 | Semiconductor devices having low contact resistance and low current leakage | Qing Liu, Chun-Chen Yeh, Ruilong Xie | 2018-08-28 |
| 10032884 | Unmerged epitaxial process for FinFET devices with aggressive fin pitch scaling | Kangguo Cheng, Ali Khakifirooz, Ruilong Xie, Tenko Yamashita | 2018-07-24 |
| 10032912 | Semiconductor integrated structure having an epitaxial SiGe layer extending from silicon-containing regions formed between segments of oxide regions | Pierre Morin, Kangguo Cheng, Jody A. Fronheiser, Juntao Li, Shogo Mochizuki +3 more | 2018-07-24 |
| 10014379 | Methods of forming semiconductor device with self-aligned contact elements and the resulting device | Ruilong Xie | 2018-07-03 |
| 10014299 | Field effect transistor device spacers | Sanjay C. Mehta, Tenko Yamashita | 2018-07-03 |
| 10008415 | Gate structure cut after formation of epitaxial active regions | Kangguo Cheng, Johnathan E. Faltermeier, Ali Khakifirooz, Theodorus E. Standaert, Ruilong Xie | 2018-06-26 |
| 9985135 | Replacement low-k spacer | Kangguo Cheng, Ali Khakifirooz, Ruilong Xie | 2018-05-29 |
| 9941388 | Method and structure for protecting gates during epitaxial growth | Ying Hao Hsieh | 2018-04-10 |
| 9935201 | High doped III-V source/drain junctions for field effect transistors | Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh | 2018-04-03 |
| 9935179 | Method for making semiconductor device with filled gate line end recesses | Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh | 2018-04-03 |
| 9929253 | Method for making a semiconductor device with sidewal spacers for confinig epitaxial growth | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2018-03-27 |
| 9922883 | Method for making strained semiconductor device and related methods | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2018-03-20 |
| 9917195 | High doped III-V source/drain junctions for field effect transistors | Qing Liu, Kejia Wang, Ruilong Xie, Chun-Chen Yeh | 2018-03-13 |
| 9892926 | Replacement low-k spacer | Kangguo Cheng, Ali Khakifirooz, Ruilong Xie | 2018-02-13 |
| 9887196 | FinFET including tunable fin height and tunable fin width ratio | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2018-02-06 |
| 9859423 | Hetero-channel FinFET | Qing Liu, Ruilong Xie, Chun-Chen Yeh | 2018-01-02 |