Issued Patents All Time
Showing 26–50 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8241973 | Method for increasing penetration depth of drain and source implantation species for a given gate height | Uwe Griebenow, Kai Frohberg, Frank Feustel | 2012-08-14 |
| 8216927 | Method of reducing contamination by providing a removable polymer protection film during microstructure processing | Ralf Richter, Frank Feustel, Kai Frohberg | 2012-07-10 |
| 8198147 | Superior fill conditions in a replacement gate approach by using a tensile stressed overlayer | Frank Feustel, Kai Frohberg | 2012-06-12 |
| 8105962 | Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach | Kai Frohberg, Frank Feustel, Uwe Griebenow | 2012-01-31 |
| 8080866 | 3-D integrated semiconductor device comprising intermediate heat spreading capabilities | Michael Grillberger, Frank Feustel | 2011-12-20 |
| 8048736 | Semiconductor device comprising a capacitor in the metallization system and a method of forming the capacitor | Frank Feustel, Kai Frohberg | 2011-11-01 |
| 8048796 | Microstructure device including a metallization structure with self-aligned air gaps formed based on a sacrificial material | Robert Seidel | 2011-11-01 |
| 8048811 | Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material | Frank Feustel, Juergen Boemmels | 2011-11-01 |
| 8040497 | Method and test structure for estimating focus settings in a lithography process based on CD measurements | Frank Feustel, Kai Frohberg | 2011-10-18 |
| 8030209 | Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer | Kai Frohberg, Frank Feustel | 2011-10-04 |
| 7989352 | Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics | Frank Feustel, Kai Frohberg | 2011-08-02 |
| 7977237 | Fabricating vias of different size of a semiconductor device by splitting the via patterning process | Frank Feustel, Kai Frohberg | 2011-07-12 |
| 7955962 | Method of reducing contamination by providing a removable polymer protection film during microstructure processing | Ralf Richter, Frank Feustel, Kai Frohberg | 2011-06-07 |
| 7951677 | Corner rounding in a replacement gate approach based on a sacrificial fill material applied prior to work function metal deposition | Jens Heinrich, Frank Seliger, Frank Richter | 2011-05-31 |
| 7932166 | Field effect transistor having a stressed contact etch stop layer with reduced conformality | Kai Frohberg, Frank Feustel | 2011-04-26 |
| 7902581 | Semiconductor device comprising a contact structure based on copper and tungsten | Kai Frohberg, Carsten Peters | 2011-03-08 |
| 7871941 | Method for reducing resist poisoning during patterning of stressed nitrogen-containing layers in a semiconductor device | Kai Frohberg, Ralf Richter | 2011-01-18 |
| 7833874 | Technique for forming an isolation trench as a stress source for strain engineering | Kai Frohberg, Patrick Press | 2010-11-16 |
| 7800106 | Test structure for OPC-related shorts between lines in a semiconductor device | Frank Feustel, Kai Frohberg | 2010-09-21 |
| 7764078 | Test structure for monitoring leakage currents in a metallization layer | Frank Feustel, Carsten Peters | 2010-07-27 |
| 7763476 | Test structure for determining characteristics of semiconductor alloys in SOI transistors by x-ray diffraction | Kai Frohberg, Holger Schuehrer | 2010-07-27 |
| 7763547 | Technique for enhancing process flexibility during the formation of vias and trenches in low-k interlayer dielectrics | Matthias Schaller, Massud Aminpur | 2010-07-27 |
| 7705352 | Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in vias | Frank Feustel, Kai Frohberg | 2010-04-27 |
| 7622391 | Method of forming an electrically conductive line in an integrated circuit | Kai Frohberg, Ruo Qing Su | 2009-11-24 |
| 7608912 | Technique for creating different mechanical strain in different CPU regions by forming an etch stop layer having differently modified intrinsic stress | Kai Frohberg, Joerg Hohage | 2009-10-27 |