Issued Patents All Time
Showing 26–50 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10971583 | Gate cut isolation including air gap, integrated circuit including same and related method | Hong Yu, Hui Zang | 2021-04-06 |
| 10964599 | Multi-step insulator formation in trenches to avoid seams in insulators | Asli Sirman, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu | 2021-03-30 |
| 10943814 | Etch stop member in buried insulator of SOI substrate to reduce contact edge punch through | Ryan Sporer | 2021-03-09 |
| 10937685 | Diffusion break structures in semiconductor devices | Sipeng Gu, Haiting Wang | 2021-03-02 |
| 10923469 | Vertical resistor adjacent inactive gate over trench isolation | Hui Zang, Guowei Xu, Ruilong Xie, Yurong Wen, Garo Derderian +2 more | 2021-02-16 |
| 10896853 | Mask-free methods of forming structures in a semiconductor device | Rinus Tek Po Lee, Wei Hong, Hui Zang, Hong Yu | 2021-01-19 |
| 10840245 | Semiconductor device with reduced parasitic capacitance | Shesh Mani Pandey, Haiting Wang | 2020-11-17 |
| 10833171 | Spacer structures on transistor devices | Yanping Shen, Hui Zang | 2020-11-10 |
| 10832839 | Metal resistors with a non-planar configuration | Scott Beasor, Haiting Wang, Sipeng Gu | 2020-11-10 |
| 10833067 | Metal resistor structure in at least one cavity in dielectric over TS contact and gate structure | Haiting Wang, Sipeng Gu, Scott Beasor, Zhenyu Hu | 2020-11-10 |
| 10811411 | Fin-type field effect transistor with reduced fin bulge and method | Bharat Krishnan | 2020-10-20 |
| 10811409 | Method of manufacturing FinFET with reduced parasitic capacitance and FinFET structure formed thereby | Hui Zang, Guowei Xu, Jian Gao | 2020-10-20 |
| 10797046 | Resistor structure for integrated circuit, and related methods | Hui Zang | 2020-10-06 |
| 10784195 | Electrical fuse formation during a multiple patterning process | Xiaoqiang Zhang, Haizhou Yin, Moosung Chae, Jinping Liu, Hui Zang | 2020-09-22 |
| 10777637 | Integrated circuit product with a multi-layer single diffusion break and methods of making such products | Hong Yu, Hui Zang | 2020-09-15 |
| 10714376 | Method of forming semiconductor material in trenches having different widths, and related structures | Chih-Chiang Chang, Haifeng Sheng, Haigou Huang, Pei Liu, Jinping Liu +2 more | 2020-07-14 |
| 10714422 | Anti-fuse with self aligned via patterning | Xiaoqiang Zhang, Guoxiang Ning | 2020-07-14 |
| 10699957 | Late gate cut using selective dielectric deposition | Hui Zang, Ruilong Xie, Chanro Park, Laertis Economikos | 2020-06-30 |
| 10692812 | Interconnects with variable space mandrel cuts formed by block patterning | Ravi Prakash Srivastava, Hui Zang | 2020-06-23 |
| 10685840 | Gate structures | Hui Zang | 2020-06-16 |
| 10629707 | FinFET structure with bulbous upper insulative cap portion to protect gate height, and related method | Hui Zang, Ruilong Xie | 2020-04-21 |
| 10593757 | Integrated circuits having converted self-aligned epitaxial etch stop | Ruilong Xie, Hui Zang, Haiting Wang | 2020-03-17 |
| 10586860 | Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process | Laertis Economikos, Xusheng Wu, John H. Zhang, Haigou Huang, Hui Zhan +4 more | 2020-03-10 |
| 10573753 | Oxide spacer in a contact over active gate finFET and method of production thereof | Hui Zang, Laertis Economikos, Ruilong Xie | 2020-02-25 |
| 10566195 | Multiple patterning with variable space mandrel cuts | Jinping Liu, Rui Chen | 2020-02-18 |