Issued Patents All Time
Showing 26–48 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9768230 | High rectifying ratio diode | Eng Huat Toh | 2017-09-19 |
| 9735164 | Low power embedded one-time programmable (OTP) structures | Ping Zheng, Eng Huat Toh, Kiok Boone Elgin Quek | 2017-08-15 |
| 9728721 | Resistive memory device | Shyue Seng Tan, Eng Huat Toh, Xuan Anh Tran, Elgin Quek | 2017-08-08 |
| 9646963 | Integrated circuits with capacitors and methods for producing the same | Shyue Seng Tan, Kiok Boone Elgin Quek | 2017-05-09 |
| 9614086 | Conformal source and drain contacts for multi-gate field effect transistors | Yee-Chia Yeo, Carlos H. Diaz, Chih-Hao Wang, Ling-Yen Yeh | 2017-04-04 |
| 9608081 | Simple and cost-free MTP structure | Shyue Seng Tan | 2017-03-28 |
| 9406764 | Simple and cost-free MTP structure | Danny Pak-Chum Shum, Yong Wee Francis Poh, Upinder Singh, Myo Aung Maung Maung | 2016-08-02 |
| 9397146 | Vertical random access memory with selectors | Eng Huat Toh, Elgin Quek, Shyue Seng Tan, Xuan Anh Tran | 2016-07-19 |
| 9153662 | MOSFET with selective dopant deactivation underneath gate | Dhanyakumar Mahaveer Sathaiya, Kai-Chieh Yang, Wei-Hao Wu, Ken-Ichi Goto, Zhiqiang Wu | 2015-10-06 |
| 9123553 | Method and system for bonding 3D semiconductor device | Chung-Shi Liu, Chen-Hua Yu, Yuh-Jier Mii | 2015-09-01 |
| 8759875 | Vertical nanowire based hetero-structure split gate memory | Ping Zheng, Eng Huat Toh | 2014-06-24 |
| 8048717 | Method and system for bonding 3D semiconductor devices | Chung-Shi Liu, Chen-Hua Yu, Yuh-Jier Mii | 2011-11-01 |
| 7612364 | MOS devices with source/drain regions having stressed regions and non-stressed regions | Harry-Hak-Lay Chuang, Kong-Beng Thei | 2009-11-03 |
| 6774463 | Superconductor gate semiconductor channel field effect transistor | Praveen Chaudhari, Richard J. Gambino, Eti Ganin, Roger Koch, Lia Krusin-Elbaum +3 more | 2004-08-10 |
| 6245639 | Method to reduce a reverse narrow channel effect for MOSFET devices | Chaochieh Tsai | 2001-06-12 |
| 6083824 | Borderless contact | Chao-Chieh Tsai, Chin-Hsiung Ho | 2000-07-04 |
| 6020255 | Dual damascene interconnect process with borderless contact | Chao-Chieh Tsai, Chin-Hsiung Ho | 2000-02-01 |
| 5801444 | Multilevel electronic structures containing copper layer and copper-semiconductor layers | Mohamed O. Aboelfotoh, Lia Krusin-Elbaum | 1998-09-01 |
| 5780327 | Vertical double-gate field effect transistor | Jack O. Chu, Louis L. Hsu, Jack A. Mandelman, Yuan Taur | 1998-07-14 |
| 5689127 | Vertical double-gate field effect transistor | Jack O. Chu, Louis L. Hsu, Jack A. Mandelman, Yuan Taur | 1997-11-18 |
| 5461250 | SiGe thin film or SOI MOSFET and method for making the same | Joachim Norbert Burghartz, Bernard S. Meyerson | 1995-10-24 |
| 5117271 | Low capacitance bipolar junction transistor and fabrication process therfor | James H. Comfort, Tze-Chiang Chen, Pong-Fei Lu, Bernard S. Meyerson, Denny Tang | 1992-05-26 |
| 5106767 | Process for fabricating low capacitance bipolar junction transistor | Janes H. Comfort, Tze-Chiang Chen, Pong-Fei Lu, Bernard S. Meyerson, Denny Tang | 1992-04-21 |