Issued Patents All Time
Showing 101–125 of 142 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5910669 | Field effect Trench transistor having lightly doped epitaxial region on the surface portion thereof | Mike F. Chang, Sze-Hon Kwan, King Owyang | 1999-06-08 |
| 5907776 | Method of forming a semiconductor structure having reduced threshold voltage and high punch-through tolerance | Koon Chong So | 1999-05-25 |
| 5907169 | Self-aligned and process-adjusted high density power transistor with gate sidewalls provided with punch through prevention and reduced JFET resistance | True-Lon Lin, Koon Chong So | 1999-05-25 |
| 5904525 | Fabrication of high-density trench DMOS using sidewall spacers | Yueh-Se Ho, Bosco Lan, Jowei Dun | 1999-05-18 |
| 5895951 | MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches | Koon Chong So, Yan Man Tsui, True-Lon Lin, Danny Chi Nim | 1999-04-20 |
| 5894150 | Cell density improvement in planar DMOS with farther-spaced body regions and novel gates | — | 1999-04-13 |
| 5883416 | Gate-contact structure to prevent contact metal penetration through gate layer without affecting breakdown voltage | True-Lon Lin, Koon Chong So, Yan Man Tsui | 1999-03-16 |
| 5883410 | Edge wrap-around protective extension for covering and protecting edges of thick oxide layer | Koon Chong So, Danny Chi Nim, Yan Man Tsui | 1999-03-16 |
| 5877529 | Mosfet termination design and core cell configuration to increase breakdown voltage and to improve device ruggedness | Koon Chong So, Danny Chi Nim, Yan Man Tsui, True-Lon Lin, Shu-Hui Cheng | 1999-03-02 |
| 5844277 | Power MOSFETs and cell topology | True-Lon Lin | 1998-12-01 |
| 5821583 | Trenched DMOS transistor with lightly doped tub | Lih-Ying Ching, Hoang H. Tran, Mike F. Chang | 1998-10-13 |
| 5770503 | Method of forming low threshold voltage vertical power transistor using epitaxial technology | Hamza Yilmaz, Mike F. Chang | 1998-06-23 |
| 5767578 | Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation | Mike F. Chang, King Owyang, Yueh-Se Ho, Jowei Dun, Hans-Jurgen Fusser +1 more | 1998-06-16 |
| 5763914 | Cell topology for power transistors with increased packing density | Danny Chi Nim | 1998-06-09 |
| 5757081 | Surface mount and flip chip technology for total integrated circuit isolation | Mike F. Chang, King Owyang, Yueh-Se Ho, Jowei Dun | 1998-05-26 |
| 5753529 | Surface mount and flip chip technology for total integrated circuit isolation | Mike F. Chang, King Owyang, Yueh-Se Ho, Jowei Dun | 1998-05-19 |
| 5750416 | Method of forming a lateral field effect transistor having reduced drain-to-source on-resistance | Mike F. Chang, Jan Van Der Linde, Yueh-Se Ho | 1998-05-12 |
| 5747853 | Semiconductor structure with controlled breakdown protection | Koon Chong So, Danny Chi Nim, True-Lon Line, Yan Man Ysui | 1998-05-05 |
| 5731611 | MOSFET transistor cell manufactured with selectively implanted punch through prevent and threshold reductoin zones | True-Lon Lin | 1998-03-24 |
| 5729037 | MOSFET structure and fabrication process for decreasing threshold voltage | Yan Man Tsui, True-Lon Lin, Danny Chi Nim, Koon Chong So | 1998-03-17 |
| 5689128 | High density trenched DMOS transistor | Mike F. Chang, Kuo-In Chen, Richard K. Williams, Mohamed N. Darwish | 1997-11-18 |
| 5668026 | DMOS fabrication process implemented with reduced number of masks | True-Lon Lin, Danny Chi Nim, Koon Chong So, Yan Man Tsui | 1997-09-16 |
| 5639676 | Trenched DMOS transistor fabrication having thick termination region oxide | Mike F. Chang, Yueh-Se Ho, King Owyang | 1997-06-17 |
| 5629543 | Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness | Mike F. Chang, Lih-Ying Ching, Sze Him Ng, William H. Cook | 1997-05-13 |
| 5614751 | Edge termination structure for power MOSFET | Hamza Yilmaz | 1997-03-25 |