Issued Patents All Time
Showing 76–100 of 142 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6420768 | Trench schottky barrier rectifier and method of making the same | Koon Chong So, John Amato | 2002-07-16 |
| 6404025 | MOSFET power device manufactured with reduced number of masks by fabrication simplified processes | Yan Man Tsui | 2002-06-11 |
| 6376315 | Method of forming a trench DMOS having reduced threshold voltage | Koon Chong So | 2002-04-23 |
| 6312993 | High speed trench DMOS | Koon Chong So | 2001-11-06 |
| 6281547 | Power transistor cells provided with reliable trenched source contacts connected to narrower source manufactured without a source mask | Koon Chong So | 2001-08-28 |
| 6262453 | Double gate-oxide for reducing gate-drain capacitance in trenched DMOS with high-dopant concentration buried-region under trenched gate | — | 2001-07-17 |
| 6172398 | Trenched DMOS device provided with body-dopant redistribution-compensation region for preventing punch through and adjusting threshold voltage | — | 2001-01-09 |
| 6144039 | Low melting pads for instant electrical connections | — | 2000-11-07 |
| 6104060 | Cost savings for manufacturing planar MOSFET devices achieved by implementing an improved device structure and fabrication process eliminating passivation layer and/or field plate | True-Lon Lin | 2000-08-15 |
| 6069043 | Method of making punch-through field effect transistor | Brian H. Floyd, Mike F. Chang | 2000-05-30 |
| 6051468 | Method of forming a semiconductor structure with uniform threshold voltage and punch-through tolerance | — | 2000-04-18 |
| 6048759 | Gate/drain capacitance reduction for double gate-oxide DMOS without degrading avalanche breakdown | Koon Chong So, Yan Man Tsui, Danny Chi Nim | 2000-04-11 |
| 6049104 | MOSFET device to reduce gate-width without increasing JFET resistance | Shang-Lin Weng, David Koh, Chanh Ly | 2000-04-11 |
| 6046078 | Semiconductor device fabrication with reduced masking steps | Koon Chong So | 2000-04-04 |
| 6031265 | Enhancing DMOS device ruggedness by reducing transistor parasitic resistance and by inducing breakdown near gate runners and termination area | — | 2000-02-29 |
| 6025230 | High speed MOSFET power device with enhanced ruggedness fabricated by simplified processes | Koon Chong So | 2000-02-15 |
| 6005271 | Semiconductor cell array with high packing density | — | 1999-12-21 |
| 5986304 | Punch-through prevention in trenched DMOS with poly-silicon layer covering trench corners | Koon Chong So, True-Lon Lin | 1999-11-16 |
| 5981344 | Trench field effect transistor with reduced punch-through susceptibility and low R.sub.DSon | Mike F. Chang | 1999-11-09 |
| 5973361 | DMOS transistors with diffusion merged body regions manufactured with reduced number of masks and enhanced ruggedness | Kong Chong So, Danny Chi Nim | 1999-10-26 |
| 5960275 | Power MOSFET fabrication process to achieve enhanced ruggedness, cost savings, and product reliability | Koon Chong So | 1999-09-28 |
| 5930630 | Method for device ruggedness improvement and on-resistance reduction for power MOSFET achieved by novel source contact structure | Kong Chong So, Danny Chi Nim | 1999-07-27 |
| 5929481 | High density trench DMOS transistor with trench bottom implant | Brian H. Floyd, Mike F. Chang, Danny Chi Nim, Daniel Ng | 1999-07-27 |
| 5923065 | Power MOSFET device manufactured with simplified fabrication processes to achieve improved ruggedness and product cost savings | Koon Chong So, Danny Chi Nim, True-Lon Lin, Yan Man Tsui | 1999-07-13 |
| 5917216 | Trenched field effect transistor with PN depletion barrier | Brian H. Floyd, Dorman C. Pitzer, Mike F. Chang | 1999-06-29 |