Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9165866 | Stacked dual chip package having leveling projections | Hamza Yilmaz, Xiaotian Zhang, Yan Xun Xue, Anup Bhalla, Jun Lu +2 more | 2015-10-20 |
| 8581376 | Stacked dual chip package and method of fabrication | Hamza Yilmaz, Xiaotian Zhang, Yan Xun Xue, Anup Bhalla, Jun Lu +2 more | 2013-11-12 |
| 7094640 | Method of making a trench MOSFET device with improved on-resistance | Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui | 2006-08-22 |
| 7049194 | Trench DMOS device with improved drain contact | Fwu-Iuan Hshieh, Koon Chong So, William John Nelson | 2006-05-23 |
| 7015125 | Trench MOSFET device with polycrystalline silicon source contact structure | Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui | 2006-03-21 |
| 6977203 | Method of forming narrow trenches in semiconductor substrates | Fwu-Iuan Hshieh, Koon Chong So, Brian Pratt | 2005-12-20 |
| 6822288 | Trench MOSFET device with polycrystalline silicon source contact structure | Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui | 2004-11-23 |
| 6657254 | Trench MOSFET device with improved on-resistance | Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui | 2003-12-02 |
| 6657255 | Trench DMOS device with improved drain contact | Fwu-Iuan Hshieh, Koon Chong So, William John Nelson | 2003-12-02 |
| 6645815 | Method for forming trench MOSFET device with low parasitic resistance | Fwu-Iuan Hshieh, Koon Chong So, Brian Pratt | 2003-11-11 |
| 6630402 | Integrated circuit resistant to the formation of cracks in a passivation layer | Fwu-Iuan Hshieh, Koon Chong So | 2003-10-07 |
| 6558984 | Trench schottky barrier rectifier and method of making the same | Fwu-Iuan Hshieh, Koon Chong So | 2003-05-06 |
| 6420768 | Trench schottky barrier rectifier and method of making the same | Fwu-Iuan Hshieh, Koon Chong So | 2002-07-16 |
| 6248651 | Low cost method of fabricating transient voltage suppressor semiconductor devices or the like | Jack Eng, Joseph Chan, Gregory Zakaluk, Dennis Garbis | 2001-06-19 |
| 5882986 | Semiconductor chips having a mesa structure provided by sawing | Jack Eng, Joseph Chan, Willem G. Einthoven, Sandy Tan, Lawrence LaTerza +2 more | 1999-03-16 |
| 5640043 | High voltage silicon diode with optimum placement of silicon-germanium layers | Jack Eng, Joseph Chan, Lawrence LaTerza, Gregory Zakaluk, Jun Wu +2 more | 1997-06-17 |
| 5635414 | Low cost method of fabricating shallow junction, Schottky semiconductor devices | Gregory Zakaluk, Dennis Garbis, Willem G. Einthoven, Joseph Chan, Jack Eng +1 more | 1997-06-03 |