Issued Patents All Time
Showing 51–75 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6323047 | Method for monitoring second gate over-etch in a semiconductor device | John Jianshi Wang, Kent Kuohua Chang | 2001-11-27 |
| 6316293 | Method of forming a nand-type flash memory device having a non-stacked gate transistor structure | — | 2001-11-13 |
| 6312991 | Elimination of poly cap easy poly 1 contact for NAND product | John Jianshi Wang, Masaaki Higashitani | 2001-11-06 |
| 6306706 | Method and system for fabricating a flash memory array | Maria C. Chan, Mark S. Chang | 2001-10-23 |
| 6300658 | Method for reduced gate aspect ration to improve gap-fill after spacer etch | John Jianshi Wang, Kent Kuohua Chang, Lu You | 2001-10-09 |
| 6235586 | Thin floating gate and conductive select gate in situ doped amorphous silicon material for NAND type flash memory device applications | Kenneth Wo-Wai Au, Kent Kuohua Chang | 2001-05-22 |
| 6228782 | Core field isolation for a NAND flash memory | Massaki Higashitani, Narbeh Derhacobian | 2001-05-08 |
| 6218689 | Method for providing a dopant level for polysilicon for flash memory devices | Kent Kuohua Chang, Kenneth Wo-Wai Au | 2001-04-17 |
| 6211058 | Semiconductor device with multiple contact sizes | John Jianshi Wang | 2001-04-03 |
| 6188113 | High voltage transistor with high gated diode breakdown, low body effect and low leakage | Narbeh Derhocobian, Pau-Ling Chen, Timothy Thurgate | 2001-02-13 |
| 6188606 | Multi state sensing of NAND memory cells by varying source bias | Narbeh Derhacobian, Michael Han | 2001-02-13 |
| 6177322 | High voltage transistor with high gated diode breakdown voltage | Narbeh Derhacobian, Pau-Ling Chen, Timothy Thurgate | 2001-01-23 |
| 6177345 | Method of silicide film formation onto a semiconductor substrate | Guarionex Morales, Jianshi Wang, Judith Quan Rizzuto | 2001-01-23 |
| 6175522 | Read operation scheme for a high-density, low voltage, and superior reliability nand flash memory device | — | 2001-01-16 |
| 6166951 | Multi state sensing of NAND memory cells by applying reverse-bias voltage | Narbeh Derhacobian, Michael Han | 2000-12-26 |
| 6159795 | Low voltage junction and high voltage junction optimization for flash memory | Masaaki Higashitani, Narbeh Derhacobian | 2000-12-12 |
| 6143608 | Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation | Yue-Song He, Masaaki Higashitani, Narbeh Derhacobian, Bill Douglas Cox, Kent Kuohua Chang +2 more | 2000-11-07 |
| 6143612 | High voltage transistor with high gated diode breakdown, low body effect and low leakage | Narbeh Derhacobian, Pau-Ling Chen, Timothy Thurgate | 2000-11-07 |
| 6133746 | Method for determining a reliable oxide thickness | Peng Fang | 2000-10-17 |
| 6072191 | Interlevel dielectric thickness monitor for complex semiconductor chips | Tho Le La, John Jianshi Wang | 2000-06-06 |
| 6057193 | Elimination of poly cap for easy poly1 contact for NAND product | John Jianshi Wang, Masaaki Higashitani | 2000-05-02 |
| 6023085 | Core cell structure and corresponding process for NAND-type high performance flash memory device | — | 2000-02-08 |
| 5994239 | Manufacturing process to eliminate polystringers in high density nand-type flash memory devices | Kent Kuohua Chang, Ken D. Au, David Chi | 1999-11-30 |
| 5994780 | Semiconductor device with multiple contact sizes | John Jianshi Wang | 1999-11-30 |
| 5991202 | Method for reducing program disturb during self-boosting in a NAND flash memory | Narbeh Derhacobian | 1999-11-23 |