Issued Patents All Time
Showing 26–50 of 83 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6667511 | NAND type core cell structure for a high density flash memory device having a unique select gate transistor configuration | — | 2003-12-23 |
| 6638358 | Method and system for processing a semiconductor device | Lu You, Mark S. Chang | 2003-10-28 |
| 6610580 | Flash memory array and a method and system of fabrication thereof | Maria C. Chan, Mark S. Chang, Mike Templeton | 2003-08-26 |
| 6602776 | Method and system for providing a polysilicon stringer monitor | Masaaki Higashitani | 2003-08-05 |
| 6603211 | Method and system for providing a robust alignment mark at thin oxide layers | Michael K. Templeton, Maria C. Chan, King Wai Kelwin Ko | 2003-08-05 |
| 6514830 | Method of manufacturing high voltage transistor with modified field implant mask | Narbeh Derhacobian | 2003-02-04 |
| 6495435 | Method for improved control of lines adjacent to a select gate using a mask assist feature | Michael K. Templeton, Maria C. Chan | 2002-12-17 |
| 6492229 | Semiconductor device having reduced field oxide recess and method of fabrication | Masaaki Higashitani, Toru Ishigaki | 2002-12-10 |
| 6472327 | Method and system for etching tunnel oxide to reduce undercutting during memory array fabrication | King Wai Kelwin Ko, Mark S. Chang | 2002-10-29 |
| 6448594 | Method and system for processing a semiconductor device | Maria C. Chan, Lu You, Mark S. Chang, King Wai Kelwin Ko | 2002-09-10 |
| 6448609 | Method and system for providing a polysilicon stringer monitor | Masaaki Higashitani | 2002-09-10 |
| 6448593 | Type-1 polysilicon electrostatic discharge transistors | Masaaki Higashitani | 2002-09-10 |
| 6445051 | Method and system for providing contacts with greater tolerance for misalignment in a flash memory | Mark S. Chang, King Wai Kelwin Ko, John Jianshi Wang, Michael K. Templeton, Lu You +1 more | 2002-09-03 |
| 6436778 | Re-oxidation approach to improve peripheral gate oxide integrity in a tunnel nitride oxidation process | Yue-Song He | 2002-08-20 |
| 6429479 | Nand flash memory with specified gate oxide thickness | K. Michael Han, Masaaki Higashitani | 2002-08-06 |
| 6420240 | Method for reducing the step height of shallow trench isolation structures | Wenge Yang, John Jianshi Wang | 2002-07-16 |
| 6417990 | Composite core structure for high efficiency writer | Yuming Zhou, Nurul Amin | 2002-07-09 |
| 6410949 | Flash memory device with monitor structure for monitoring second gate over-etch | John Jianshi Wang, Kent Kuohua Chang | 2002-06-25 |
| 6376309 | Method for reduced gate aspect ratio to improve gap-fill after spacer etch | John Jianshi Wang, Kent Kuohua Chang, Lu You | 2002-04-23 |
| 6372577 | Core cell structure and corresponding process for NAND type performance flash memory device | — | 2002-04-16 |
| 6369433 | High voltage transistor with low body effect and low leakage | Narbeh Derhacobian, Pau-Ling Chen | 2002-04-09 |
| 6362049 | High yield performance semiconductor process flow for NAND flash memory products | Salvatore F. Cagnina, John Jianshi Wang, Kent Kuohua Chang, Masaatzi Higashitani | 2002-03-26 |
| 6350627 | Interlevel dielectric thickness monitor for complex semiconductor chips | Tho Le La, John Jianshi Wang | 2002-02-26 |
| 6351017 | High voltage transistor with modified field implant mask | Narbeh Derhacobian | 2002-02-26 |
| 6346737 | Shallow trench isolation process particularly suited for high voltage circuits | Masaaki Higashitani | 2002-02-12 |