YC

Yung Fu Chong

CM Chartered Semiconductor Manufacturing: 29 patents #20 of 840Top 3%
GP Globalfoundries Singapore Pte.: 18 patents #33 of 828Top 4%
IBM: 17 patents #6,502 of 70,183Top 10%
NS National University Of Singapore: 3 patents #115 of 1,623Top 8%
Infineon Technologies Ag: 3 patents #2,452 of 7,486Top 35%
Samsung: 2 patents #37,631 of 75,807Top 50%
NU Nanyang Technological University: 1 patents #385 of 1,285Top 30%
IM Institute Of Microelectronics: 1 patents #60 of 153Top 40%
📍 Singapore, SG: #72 of 13,971 inventorsTop 1%
Overall (All Time): #56,172 of 4,157,543Top 2%
49
Patents All Time

Issued Patents All Time

Showing 26–49 of 49 patents

Patent #TitleCo-InventorsDate
7718500 Formation of raised source/drain structures in NFET with embedded SiGe in PFET Zhijiong Luo, Joo-chan Kim, Judson R. Holt 2010-05-18
7692213 Integrated circuit system employing a condensation process Lee-Wee Teo, Elgin Quek, Alain Chan 2010-04-06
7645687 Method to fabricate variable work function gates for FUSI devices Dong Kyun Sohn, Chew-Hue Ang, Purakh Raj Vermo, Liang-Choo Hsia 2010-01-12
7595233 Gate stress engineering for MOSFET Zhijiong Luo, Huilong Zhu 2009-09-29
7572712 Method to form selective strained Si using lateral epitaxy Zhijiong Luo, Judson R. Holt 2009-08-11
7566609 Method of manufacturing a semiconductor structure Zhijiong Luo, Huilong Zhu 2009-07-28
7485524 MOSFETs comprising source/drain regions with slanted upper surfaces, and method for fabricating the same Zhijiong Luo, Judson R. Holt, Zhao Lun, Huilong Zhu 2009-02-03
7482656 Method and structure to form self-aligned selective-SOI Zhijiong Luo, Kevin K. Dezfulian, Huilong Zhu, Judson R. Holt 2009-01-27
7442618 Method to engineer etch profiles in Si substrate for advanced semiconductor devices Brian J. Greene, Siddhartha Panda, Nivo Rovedo 2008-10-28
7442619 Method of forming substantially L-shaped silicide contact for a semiconductor device Zhijiong Luo, Huilong Zhu, Hung Y. Ng, Kern Rim, Nivo Rovedo 2008-10-28
7413961 Method of fabricating a transistor structure Kevin K. Dezfulian, Zhijiong Luo, Huilong Zhu 2008-08-19
7405131 Method and structure to prevent silicide strapping of source/drain to body in semiconductor devices with source/drain stressor Brian J. Greene 2008-07-29
7326609 Semiconductor device and fabrication method Purakh Raj Verma, Liang-Choo Hsia, Dong Kyun Sohn, Guowei Zhang, Chew Hoe Ang +3 more 2008-02-05
7256112 Laser activation of implanted contact plug for memory bitline fabrication Dong Kyun Sohn, Liang-Choo Hsia 2007-08-14
6734072 Method of fabricating a MOSFET device using a spike rapid thermal oxidation procedure Alex See 2004-05-11
6727151 Method to fabricate elevated source/drain structures in MOS transistors Randall Cher Liang Cha, Alex See 2004-04-27
6624489 Formation of silicided shallow junctions using implant through metal technology and laser annealing process Kin Leong Pey, Alex See 2003-09-23
6566215 Method of fabricating short channel MOS transistors with source/drain extensions Lap Chan 2003-05-20
6566650 Incorporation of dielectric layer onto SThM tips for direct thermal analysis Chang Chaun Hu, Kin Leong Pey, Chim Wai Kin, Pavel Neuzil, Lap Chan 2003-05-20
6534390 Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structure Randall Cher Liang Cha, Kin Leong Pey 2003-03-18
6391731 Activating source and drain junctions and extensions using a single laser anneal Kin Leong Pey, Alex See 2002-05-21
6387784 Method to reduce polysilicon depletion in MOS transistors Randall Cher Liang Cha, Lap Chan, Kin Leong Pey 2002-05-14
6365446 Formation of silicided ultra-shallow junctions using implant through metal technology and laser annealing process Kin Leong Pey, Alex See 2002-04-02
6335253 Method to form MOS transistors with shallow junctions using laser annealing Kin Leong Pey, Alex See, Andrew Thye Shen Wee 2002-01-01