Issued Patents All Time
Showing 26–50 of 92 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6265256 | MOS transistor with minimal overlap between gate and source/drain extensions | Judy Xilin An, Bin Yu | 2001-07-24 |
| 6232632 | Double density non-volatile memory cells | — | 2001-05-15 |
| 6225161 | Fully recessed semiconductor method for low power applications with single wrap around buried drain region | Donald L. Wollesen | 2001-05-01 |
| 6225669 | Non-uniform gate/dielectric field effect transistor | Wei Long, Don Wollesen | 2001-05-01 |
| 6225659 | Trenched gate semiconductor device and method for low power applications | — | 2001-05-01 |
| 6211692 | Method and apparatus for determining the robustness and incident angle sensitivity of memory cells to alpha-particle/cosmic ray induced soft errors | Sunil N. Shabde | 2001-04-03 |
| 6208154 | Method of determining the doping concentration across a surface of a semiconductor material | Sunil N. Shabde, Ting Tsui | 2001-03-27 |
| 6184105 | Method for post transistor isolation | Sunil Mehta | 2001-02-06 |
| 6184108 | Method of making trench isolation structures with oxidized silicon regions | Farrokh Omid-Zohoor | 2001-02-06 |
| 6180441 | Bar field effect transistor | John T. Yue, Matthew S. Buynoski, Peng Fang | 2001-01-30 |
| 6177802 | System and method for detecting defects in an interlayer dielectric of a semiconductor device using the hall-effect | Sunil N. Shabde, Ting Tsui | 2001-01-23 |
| 6169302 | Determination of parasitic capacitance between the gate and drain/source local interconnect of a field effect transistor | Wei Long, Qi Xiang | 2001-01-02 |
| 6166558 | Method for measuring gate length and drain/source gate overlap | Chun Jiang, Wei Long, Zicheng Gary Ling | 2000-12-26 |
| 6163052 | Trench-gated vertical combination JFET and MOSFET devices | Donald L. Wollesen | 2000-12-19 |
| 6153534 | Method for fabricating a dual material gate of a short channel field effect transistor | Wei Long, Qi Xiang | 2000-11-28 |
| 6147507 | System and method of mapping leakage current and a defect profile of a semiconductor dielectric layer | Sunil N. Shabde, Ting Tsui | 2000-11-14 |
| 6146973 | High density isolation using an implant as a polish stop | Yue-Song He | 2000-11-14 |
| 6147377 | Fully recessed semiconductor device | — | 2000-11-14 |
| 6147378 | Fully recessed semiconductor device and method for low power applications with single wrap around buried drain region | Donald L. Wollesen | 2000-11-14 |
| 6124608 | Non-volatile trench semiconductor device having a shallow drain region | Yu Sun, Donald L. Wollesen | 2000-09-26 |
| 6118147 | Double density non-volatile memory cells | — | 2000-09-12 |
| 6107667 | MOS transistor with low-k spacer to suppress capacitive coupling between gate and source/drain extensions | Judy Xilin An, Bin Yu | 2000-08-22 |
| 6097061 | Trenched gate metal oxide semiconductor device and method | Donald L. Wollesen | 2000-08-01 |
| 6093967 | Self-aligned silicide contacts formed from deposited silicon | Mark S. Chang, Michael K. Templeton | 2000-07-25 |
| 6069485 | C-V method to extract lateral channel doping profiles of MOSFETs | Wei Long, Chun Jiang | 2000-05-30 |