YL

Yowjuang W. Liu

AM AMD: 89 patents #38 of 9,279Top 1%
IN Intel: 3 patents #10,349 of 30,777Top 35%
📍 San Jose, CA: #306 of 32,062 inventorsTop 1%
🗺 California: #2,615 of 386,348 inventorsTop 1%
Overall (All Time): #17,300 of 4,157,543Top 1%
92
Patents All Time

Issued Patents All Time

Showing 76–92 of 92 patents

Patent #TitleCo-InventorsDate
5874328 Reverse CMOS method for dual isolation semiconductor device Kuang-Yeh Chang 1999-02-23
5864158 Trench-gated vertical CMOS device Donald L. Wollesen 1999-01-26
5838044 Integrated circuit having improved polysilicon resistor structures Kuang-Yeh Chang 1998-11-17
5821146 Method of fabricating FET or CMOS transistors using MeV implantation Kuang-Yeh Chang, Mark I. Gardner, Fred N. Hause 1998-10-13
5777370 Trench isolation of field effect transistors Farrokh Omid-Zohoor, Andre Stolmeijer, Craig S. Sander 1998-07-07
5739063 High temperature local oxidation of silicon for fine line patterns Yu Sun 1998-04-14
5734179 SRAM cell having single layer polysilicon thin film transistors Kuang-Yeh Chang 1998-03-31
5712173 Method of making semiconductor device with self-aligned insulator Feng Qian, Tze-Kwai Kelvin Lai 1998-01-27
5693568 Reverse damascene via structures Kuang-Yeh Chang 1997-12-02
5672524 Three-dimensional complementary field effect transistor process Yu Sun 1997-09-30
5646063 Hybrid of local oxidation of silicon isolation and trench isolation for a semiconductor device Sunil Mehta 1997-07-08
5612249 Post-gate LOCOS Yu Sun 1997-03-18
5610088 Method of fabricating field effect transistors having lightly doped drain regions Kuang-Yeh Chang 1997-03-11
5608253 Advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits Kuang-Yeh Chang 1997-03-04
5554562 Advanced isolation scheme for deep submicron technology Kuang-Yeh Chang, Mark I. Gardner, Frederick N. Hause 1996-09-10
5489540 Method of making simplified LDD and source/drain formation in advanced CMOS integrated circuits using implantation through well mask Kuang-Yeh Chang 1996-02-06
5091324 Process for producing optimum intrinsic, long channel, and short channel MOS devices in VLSI structures James Hsu 1992-02-25