Issued Patents All Time
Showing 26–50 of 58 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9419911 | Method and system for packet job scheduler in data processing based on workload self-learning | Edward Ho, Robert Hathaway, Michael Feng, Edmund CHEN, Jayaram Beladakere | 2016-08-16 |
| 9418010 | Global maintenance command protocol in a cache coherent system | Gerard R. Williams, III | 2016-08-16 |
| 9128725 | Load-store dependency predictor content management | John H. Mylius, Gerard R. Williams, III, Suparn Vats | 2015-09-08 |
| 9116817 | Pointer chasing prediction | — | 2015-08-25 |
| 9015422 | Access map-pattern match based prefetch unit for a processor | Gerard R. Williams, III, Hari Kannan, Pavlos Konas | 2015-04-21 |
| 8656139 | Digital processor for processing long and short pointers and converting each between a common format | John G. Favor, Evan Gewirtz, Robert Hathaway, Eric M. Trehus | 2014-02-18 |
| 8402248 | Explicitly regioned memory organization in a network element | Robert Hathaway, Evan Gewirtz, Brian Alleyne, Edward Ho | 2013-03-19 |
| 8051227 | Programmable queue structures for multiprocessors | Evan Gewirtz, Robert Hathaway | 2011-11-01 |
| 7852846 | Method and apparatus for out-of-order processing of packets | John G. Favor, Edmund Chen | 2010-12-14 |
| 7818592 | Token based power control mechanism | Marius Evers | 2010-10-19 |
| 7349398 | Method and apparatus for out-of-order processing of packets | John G. Favor, Edmund Chen | 2008-03-25 |
| 7051300 | Method and system for architectural power estimation | Gene W. Shen, Leslie Barnes, Paul Keltcher | 2006-05-23 |
| 6704854 | Determination of execution resource allocation based on concurrently executable misaligned memory operations | James B. Keller | 2004-03-09 |
| 6622235 | Scheduler which retries load/store hit situations | James B. Keller, Ramsey W. Haddad | 2003-09-16 |
| 6604187 | Providing global translations with address space numbers | Kevin J. McGrath | 2003-08-05 |
| 6564315 | Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction | James B. Keller, Ramsey W. Haddad | 2003-05-13 |
| 6542984 | Scheduler capable of issuing and reissuing dependency chains | James B. Keller, Ramsey W. Haddad | 2003-04-01 |
| 6523109 | Store queue multimatch detection | — | 2003-02-18 |
| 6487653 | Method and apparatus for denormal load handling | Stuart F. Oberman, Jeffrey E. Trull | 2002-11-26 |
| 6481251 | Store queue number assignment and tracking | Ramsey W. Haddad | 2002-11-19 |
| 6442677 | Apparatus and method for superforwarding load operands in a microprocessor | Derrick R. Meyer, Norbert Juffa | 2002-08-27 |
| 6425074 | Method and apparatus for rapid execution of FCOM and FSTSW | Norbert Juffa, Frederick Daniel Weber, Stuart F. Oberman | 2002-07-23 |
| 6425072 | System for implementing a register free-list by using swap bit to select first or second register tag in retire queue | Chetana N. Keltcher | 2002-07-23 |
| 6408379 | Apparatus and method for executing floating-point store instructions in a microprocessor | Norbert Juffa, Stuart F. Oberman, Scott White | 2002-06-18 |
| 6405305 | Rapid execution of floating point load control word instructions | Jeffrey E. Trull, Derrick R. Meyer, Norbert Juffa | 2002-06-11 |