Issued Patents All Time
Showing 51–75 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6468865 | Method of simultaneous formation of bitline isolation and periphery oxide | Jean Y. Yang, Mark T. Ramsbey, Hidehiko Shiraiwa, David Michael Rogers, Ravi Sunkavalli +3 more | 2002-10-22 |
| 6470414 | Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture | Tiao-Hua Kuo, Yasushi Kasa, Nancy Leong, Johnny C. Chen | 2002-10-22 |
| 6465306 | Simultaneous formation of charge storage and bitline to wordline isolation | Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, David Michael Rogers, Ravi Sunkavalli +3 more | 2002-10-15 |
| 6292399 | Method and low-power circuits used to generate accurate drain voltage for flash memory core cells in read mode | Binh Quang Le, Pau-Ling Chen | 2001-09-18 |
| 6275894 | Bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture | Tiao-Hua Kuo, Yasushi Kasa, Nancy Leong, Johnny C. Chen | 2001-08-14 |
| 6266281 | Method of erasing non-volatile memory cells | Narbeth Derhacobian, Daniel Sobeck, Janet Wang, Chi Chang | 2001-07-24 |
| 6205074 | Temperature-compensated bias generator | Bhimachar Venkatesh | 2001-03-20 |
| 6172914 | Concurrent erase verify scheme for flash memory applications | Sameer Haddad, Colin S. Bill | 2001-01-09 |
| 6005803 | Memory address decoding circuit for a simultaneous operation flash memory device with a flexible bank partition architecture | Tiao-Hua Kuo, Yasushi Kasa, Nancy Leong, Johnny C. Chen | 1999-12-21 |
| 6001689 | Process for fabricating a flash memory with dual function control lines | Chi Chang | 1999-12-14 |
| 5995415 | Simultaneous operation flash memory device with a flexible bank partition architecture | Tiao-Hua Kuo, Yasushi Kasa, Nancy Leong, Johnny C. Chen | 1999-11-30 |
| 5978267 | Bit line biasing method to eliminate program disturbance in a non-volatile memory device and memory device employing the same | Pau-Ling Chen, Shane Hollmer, Michael Chung, Binh Quang Le, Vincent Leung +2 more | 1999-11-02 |
| 5949718 | Method and system for selected source during read and programming of flash memory | Mark Randolph, Collin Bill | 1999-09-07 |
| 5847998 | Non-volatile memory array that enables simultaneous read and write operations | — | 1998-12-08 |
| 5650964 | Method of inhibiting degradation of ultra short channel charge-carrying devices during discharge | Jian Chen, James Hsu, Shengwen Luan, Yuan Tang, David Kuan-Yu Liu | 1997-07-22 |
| 5579274 | Sense circuit for a flash eefprom cell having a negative delta threshold voltage | Michael S. Briner | 1996-11-26 |
| 5485423 | Method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMS | Yuan Tang, Chi Chang, Chung K. Chang | 1996-01-16 |
| 5477499 | Memory architecture for a three volt flash EEPROM | Michael S. Briner | 1995-12-19 |
| 5406517 | Distributed negative gate power supply | Chung K. Chang, Johnny C. Chen, Lee Cleveland | 1995-04-11 |
| 5376835 | Power-on reset circuit | Johnny C. Chen, Chung K. Chang, Lee Cleveland, Antonio Montalvo | 1994-12-27 |
| 5365484 | Independent array grounds for flash EEPROM array with paged erase architechture | Lee Cleveland, Johhny C. Chen, Chung K. Chang | 1994-11-15 |
| 5359558 | Flash eeprom array with improved high endurance | Chung K. Chang, Johnny C. Chen, Lee Cleveland | 1994-10-25 |
| 5349558 | Sector-based redundancy architecture | Lee Cleveland, Johnny C. Chen, Chung K. Chang | 1994-09-20 |
| 5335198 | Flash EEPROM array with high endurance | Kevin W. Plouse, Joseph G. Pawletko, Chi Chang, Sameer Haddad, Ravi Prakash Gutala | 1994-08-02 |
| 5291446 | VPP power supply having a regulator circuit for controlling a regulated positive potential | Johnny C. Chen, Chung K. Chang, Lee Cleveland, Antonio Montalvo | 1994-03-01 |