Issued Patents All Time
Showing 26–50 of 84 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8531878 | Techniques for providing a semiconductor memory device | Srinivasa Banna, Timothy Thurgate | 2013-09-10 |
| 8498157 | Techniques for providing a direct injection semiconductor memory device | Srinivasa Banna | 2013-07-30 |
| 8400811 | Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines | Eric Carman, Yogesh Luthra | 2013-03-19 |
| 8315099 | Techniques for providing a direct injection semiconductor memory device | Betina Hold, Wayne F. Ellis | 2012-11-20 |
| 7902086 | Prevention of oxidation of carrier ions to improve memory retention properties of polymer memory cell | Swaroop Kaza, David Gaun | 2011-03-08 |
| 7672161 | Adaptive detection of threshold levels in memory | Ping Hou, Eugen Gershon | 2010-03-02 |
| 7474579 | Use of periodic refresh in medium retention memory arrays | Colin S. Bill, Swaroop Kaza, Wei Daisy Cai, Tzu-Ning Fang, David Gaun +2 more | 2009-01-06 |
| 7443710 | Control of memory devices possessing variable resistance characteristics | Tzu-Ning Fang, Colin S. Bill | 2008-10-28 |
| 7273766 | Variable density and variable persistent organic memory devices, methods, and fabrication | Zhida Lan, Tzu-Ning Fang, Colin S. Bill, John S. Ennals | 2007-09-25 |
| 7259039 | Memory device and methods of using and making the device | Zhida Lan, Colin S. Bill | 2007-08-21 |
| 7103706 | System and method for multi-bit flash reads using dual dynamic references | Darlene Hamilton, Pua-Ling Chen, Kazuhiro Kuribara | 2006-09-05 |
| 6838869 | Clocked based method and devices for measuring voltage-variable capacitances and other on-chip parameters | David Michael Rogers, Mimi Qian, Roger Tsao | 2005-01-04 |
| 6799256 | System and method for multi-bit flash reads using dual dynamic references | Darlene Hamilton, Pua-Ling Chen, Kazuhiro Kuribara | 2004-09-28 |
| 6744668 | Flash memory array with dual function control lines and asymmetrical source and drain junctions | Chi Chang | 2004-06-01 |
| 6630384 | Method of fabricating double densed core gates in sonos flash memory | Yu Sun, Mark T. Ramsbey | 2003-10-07 |
| 6583479 | Sidewall NROM and method of manufacture thereof for non-volatile memory cells | Richard Fastow, Shane Hollmer, Pau-Ling Chen, Masaaki Higashitani | 2003-06-24 |
| 6555436 | Simultaneous formation of charge storage and bitline to wordline isolation | Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, David Michael Rogers, Ravi Sunkavalli +3 more | 2003-04-29 |
| 6549466 | Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure | Narbeh Derhacobian, Chi Chang, Daniel Sobek | 2003-04-15 |
| 6541816 | Planar structure for non-volatile memory devices | Mark T. Ramsbey, Jean Y. Yang, Hidehiko Shiraiwa, David Michael Rogers, Ravi Sunkavalli +2 more | 2003-04-01 |
| 6529412 | Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge | Pau-Ling Chen, Yu Sun | 2003-03-04 |
| 6515902 | Method and apparatus for boosting bitlines for low VCC read | Pau-Ling Chen | 2003-02-04 |
| 6510082 | Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold | Binh Quang Le, Pau-Ling Chen, Santosh Yachareni, Michael Chung, Kazuhiro Kurihara +1 more | 2003-01-21 |
| 6501681 | Using a low drain bias during erase verify to ensure complete removal of residual charge in the nitride in sonos non-volatile memories | Narbeh Derhacobian | 2002-12-31 |
| 6492675 | Flash memory array with dual function control lines and asymmetrical source and drain junctions | Chi Chang | 2002-12-10 |
| 6493261 | Single bit array edges | Darlene Hamilton, Kulachet Tanpairoj, Ravi Sunkavalli, Narbeh Derhacobian | 2002-12-10 |