Issued Patents 2024
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176429 | Wrap-around contact structures for semiconductor nanowires and nanoribbons | Tahir Ghani, Stephen M. Cea, Biswajeet Guha | 2024-12-24 |
| 12107085 | Interconnect techniques for electrically connecting source/drain regions of stacked transistors | Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Christopher J. Jezewski, Ehren Mannebach +4 more | 2024-10-01 |
| 12100623 | Vertically stacked finFETs and shared gate patterning | Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Stephen M. Cea, Patrick Morrow +1 more | 2024-09-24 |
| 12100705 | Deep trench via for three-dimensional integrated circuit | Yih Wang, Mauro J. Kobrinsky, Tahir Ghani, Mark Bohr, Marni Nabors | 2024-09-24 |
| 12057494 | Stacked transistors | Patrick Morrow, Aaron D. Lilak | 2024-08-06 |
| 12033896 | Isolation wall stressor structures to improve channel stress and their methods of fabrication | Aaron D. Lilak, Christopher J. Jezewski, Willy Rachmady, Gilbert Dewey, Anh Phan | 2024-07-09 |
| 11996362 | Integrated circuit device with crenellated metal trace layout | Patrick Morrow, Mauro J. Kobrinsky, Mark Bohr, Tahir Ghani, Ranjith Kumar | 2024-05-28 |
| 11984506 | Field effect transistor having a gate dielectric with a dipole layer and having a gate stressor layer | Vishal Tiwari, Dan S. LAVRIC, Michal Mleczko, Szuya S. Liao | 2024-05-14 |
| 11942526 | Integrated circuit contact structures | Patrick Morrow, Glenn A. Glass, Anand S. Murthy | 2024-03-26 |
| 11942416 | Sideways vias in isolation areas to contact interior layers in stacked devices | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +3 more | 2024-03-26 |
| 11935891 | Non-silicon N-type and P-type stacked transistors for integrated circuit devices | Gilbert Dewey, Patrick Morrow, Ravi Pillarisetty, Cheng-Ying Huang, Willy Rachmady +1 more | 2024-03-19 |
| 11935933 | Backside contact structures and fabrication for metal on both sides of devices | Patrick Morrow, Aaron D. Lilak, Kimin Jun | 2024-03-19 |
| 11923412 | Sub-fin leakage reduction for template strained materials | Stephen M. Cea, Anupama Bowonder, Juhyung Nam, Willy Rachmady | 2024-03-05 |
| 11901457 | Fin shaping and integrated circuit structures resulting therefrom | Szuya S. Liao, Rahul Pandey, Anupama Bowonder, Pratik A. Patel | 2024-02-13 |
| 11894262 | Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures | Aaron D. Lilak, Patrick Morrow | 2024-02-06 |
| 11869890 | Stacked transistors with contact last | Ravi Pillarisetty, Willy Rachmady, Gilbert Dewey, Jack T. Kavalieros | 2024-01-09 |
| 11862702 | Gate-all-around integrated circuit structures having insulator FIN on insulator substrate | Aaron D. Lilak, Cory E. Weber, Willy Rachmady, Varun MISHRA | 2024-01-02 |