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USPTO Patent Rankings Data through Dec 31, 2025
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Anh Phan — 11 Patents in 2024

Intel: 11 patents #119 of 4,430Top 3%
Beaverton, OR: #20 of 530 inventorsTop 4%
Oregon: #135 of 4,306 inventorsTop 4%
Overall (2024): #8,300 of 561,600Top 2%
11 Patents 2024

Issued Patents 2024

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12148806 Stacked source-drain-gate connection and process for forming such Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Willy Rachmady +2 more 2024-11-19 $25,575,000
12107085 Interconnect techniques for electrically connecting source/drain regions of stacked transistors Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Christopher J. Jezewski, Ehren Mannebach +4 more 2024-10-01 $20,560,000
12080605 Backside contacts for semiconductor devices Aaron D. Lilak, Ehren Mannebach, Richard E. Schenker, Stephanie A. Bojarski, Willy Rachmady +4 more 2024-09-03 $14,017,000
12033896 Isolation wall stressor structures to improve channel stress and their methods of fabrication Aaron D. Lilak, Christopher J. Jezewski, Willy Rachmady, Rishabh Mehandru, Gilbert Dewey 2024-07-09 $24,938,000
12020929 Epitaxial layer with substantially parallel sides Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach +3 more 2024-06-25 $22,163,000
11996411 Stacked forksheet transistors Cheng-Ying Huang, Gilbert Dewey, Nicole K. Thomas, Urusa Alaan, Seung Hoon Sung +8 more 2024-05-28 $30,739,000
11996408 Leave-behind protective layer having secondary purpose Aaron D. Lilak, Ehren Mannebach, Cheng-Ying Huang, Stephanie A. Bojarski, Gilbert Dewey +2 more 2024-05-28 $30,739,000
11942416 Sideways vias in isolation areas to contact interior layers in stacked devices Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Willy Rachmady +3 more 2024-03-26 $33,708,000
11916118 Stacked source-drain-gate connection and process for forming such Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Willy Rachmady +2 more 2024-02-27 $28,450,000
11894372 Stacked trigate transistors with dielectric isolation and process for forming such Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Aaron D. Lilak, Patrick Morrow +2 more 2024-02-06 $35,892,000
11869894 Metallization structures for stacked device connectivity and their methods of fabrication Aaron D. Lilak, Patrick Morrow, Willy Rachmady, Gilbert Dewey, Jessica M. Torres +6 more 2024-01-09 $30,329,000