EM

Ehren Mannebach

IN Intel: 10 patents #141 of 4,430Top 4%
Overall (2024): #9,726 of 561,600Top 2%
10
Patents 2024

Issued Patents 2024

Patent #TitleCo-InventorsDate
12148806 Stacked source-drain-gate connection and process for forming such Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady +2 more 2024-11-19
12107085 Interconnect techniques for electrically connecting source/drain regions of stacked transistors Aaron D. Lilak, Gilbert Dewey, Cheng-Ying Huang, Christopher J. Jezewski, Rishabh Mehandru +4 more 2024-10-01
12080605 Backside contacts for semiconductor devices Aaron D. Lilak, Anh Phan, Richard E. Schenker, Stephanie A. Bojarski, Willy Rachmady +4 more 2024-09-03
12020929 Epitaxial layer with substantially parallel sides Cheng-Ying Huang, Gilbert Dewey, Jack T. Kavalieros, Aaron D. Lilak, Patrick Morrow +3 more 2024-06-25
11996411 Stacked forksheet transistors Cheng-Ying Huang, Gilbert Dewey, Anh Phan, Nicole K. Thomas, Urusa Alaan +8 more 2024-05-28
11996408 Leave-behind protective layer having secondary purpose Aaron D. Lilak, Anh Phan, Cheng-Ying Huang, Stephanie A. Bojarski, Gilbert Dewey +2 more 2024-05-28
11942416 Sideways vias in isolation areas to contact interior layers in stacked devices Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady +3 more 2024-03-26
11916118 Stacked source-drain-gate connection and process for forming such Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady +2 more 2024-02-27
11894372 Stacked trigate transistors with dielectric isolation and process for forming such Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Aaron D. Lilak, Patrick Morrow +2 more 2024-02-06
11862636 Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach Nicole K. Thomas, Cheng-Ying Huang, Marko Radosavljevic 2024-01-02