Issued Patents 2024
Showing 25 most recent of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12183739 | Ribbon or wire transistor stack with selective dipole threshold voltage shifter | Nicole K. Thomas, Eric Mattson, Sudarat Lee, Scott B. Clendenning, Tobias Brown-Heft +6 more | 2024-12-31 |
| 12183668 | Thin-film transistors and MIM capacitors in exclusion zones | Abhishek A. Sharma, Willy Rachmady, Cheng-Ying Huang, Rajat K. Paul | 2024-12-31 |
| 12183831 | Self-aligned contacts for thin film transistors | Van H. Le, Abhishek A. Sharma, Benjamin Chu-Kung, Ravi Pillarisetty, Miriam Reshotko +4 more | 2024-12-31 |
| 12170319 | Dual contact process with stacked metal layers | Kevin T. Cook, Anand S. Murthy, Nazila Haratipour, Ralph T. Troeger, Christopher J. Jezewski +1 more | 2024-12-17 |
| 12148806 | Stacked source-drain-gate connection and process for forming such | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +2 more | 2024-11-19 |
| 12142689 | Transistor including wrap around source and drain contacts | Sean T. Ma, Abhishek A. Sharma, Jack T. Kavalieros, Van H. Le | 2024-11-12 |
| 12125917 | Thin film transistors having double gates | Abhishek A. Sharma, Van H. Le, Jack T. Kavalieros, Tahir Ghani | 2024-10-22 |
| 12119387 | Low resistance approaches for fabricating contacts and the resulting structures | Nazila Haratipour, Siddharth Chouksey, Jack T. Kavalieros, Jitendra Kumar Jha, Matthew V. Metz +6 more | 2024-10-15 |
| 12120865 | Arrays of double-sided dram cells including capacitors on the frontside and backside of a stacked transistor structure | Cheng-Ying Huang, Ashish Agrawal, Abhishek A. Sharma, Wilfred Gomes, Jack T. Kavalieros | 2024-10-15 |
| 12119409 | Multi-layer crystalline back gated thin film transistor | Van H. Le, Abhishek A. Sharma, Kent Millard, Jack T. Kavalieros, Shriram Shivaraman +6 more | 2024-10-15 |
| 12107085 | Interconnect techniques for electrically connecting source/drain regions of stacked transistors | Aaron D. Lilak, Cheng-Ying Huang, Christopher J. Jezewski, Ehren Mannebach, Rishabh Mehandru +4 more | 2024-10-01 |
| 12087750 | Stacked-substrate FPGA semiconductor devices | Abhishek A. Sharma, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros | 2024-09-10 |
| 12080605 | Backside contacts for semiconductor devices | Aaron D. Lilak, Ehren Mannebach, Anh Phan, Richard E. Schenker, Stephanie A. Bojarski +4 more | 2024-09-03 |
| 12068319 | High performance semiconductor oxide material channel regions for NMOS | Willy Rachmady, Jack T. Kavalieros, Cheng-Ying Huang, Matthew V. Metz, Sean T. Ma +3 more | 2024-08-20 |
| 12033896 | Isolation wall stressor structures to improve channel stress and their methods of fabrication | Aaron D. Lilak, Christopher J. Jezewski, Willy Rachmady, Rishabh Mehandru, Anh Phan | 2024-07-09 |
| 12020929 | Epitaxial layer with substantially parallel sides | Cheng-Ying Huang, Jack T. Kavalieros, Aaron D. Lilak, Ehren Mannebach, Patrick Morrow +3 more | 2024-06-25 |
| 12009433 | Multi-dielectric gate stack for crystalline thin film transistors | Van H. Le, Inanc Meric, Sean T. Ma, Abhishek A. Sharma, Miriam Reshotko +6 more | 2024-06-11 |
| 11996447 | Field effect transistors with gate electrode self-aligned to semiconductor fin | Sean T. Ma, Matthew V. Metz, Willy Rachmady, Chandra S. Mohapatra, Jack T. Kavalieros +2 more | 2024-05-28 |
| 11996404 | Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material | Cheng-Ying Huang, Ashish Agrawal, Kimin Jun, Willy Rachmady, Zachary Geiger +5 more | 2024-05-28 |
| 11996408 | Leave-behind protective layer having secondary purpose | Aaron D. Lilak, Anh Phan, Ehren Mannebach, Cheng-Ying Huang, Stephanie A. Bojarski +2 more | 2024-05-28 |
| 11996411 | Stacked forksheet transistors | Cheng-Ying Huang, Anh Phan, Nicole K. Thomas, Urusa Alaan, Seung Hoon Sung +8 more | 2024-05-28 |
| 11997847 | Thin film transistors with spacer controlled gate length | Abhishek A. Sharma, Van H. Le, Shriram Shivaraman, Yih Wang, Tahir Ghani +1 more | 2024-05-28 |
| 11990476 | Semiconductor nanowire device having (111)-plane channel sidewalls | Cory E. Weber, Harold W. Kennel, Willy Rachmady | 2024-05-21 |
| 11942416 | Sideways vias in isolation areas to contact interior layers in stacked devices | Ehren Mannebach, Aaron D. Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan +3 more | 2024-03-26 |
| 11935891 | Non-silicon N-type and P-type stacked transistors for integrated circuit devices | Patrick Morrow, Ravi Pillarisetty, Rishabh Mehandru, Cheng-Ying Huang, Willy Rachmady +1 more | 2024-03-19 |