Issued Patents 2024
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176429 | Wrap-around contact structures for semiconductor nanowires and nanoribbons | Rishabh Mehandru, Tahir Ghani, Stephen M. Cea | 2024-12-24 |
| 12166031 | Substrate-less electrostatic discharge (ESD) integrated circuit structures | Brian J. Greene, Daniel Schulman, William Hsu, Chung-Hsun Lin, Curtis Tsai +1 more | 2024-12-10 |
| 12159901 | Gate-all-around integrated circuit structures having source or drain structures with epitaxial nubs | Cory Bomberger, Anand S. Murthy, Mark Bohr, Tahir Ghani | 2024-12-03 |
| 12068314 | Fabrication of gate-all-around integrated circuit structures having adjacent island structures | Leonard P. GULER, William Hsu, Martin Weiss, Apratim Dhar, William T. BLANTON +7 more | 2024-08-20 |
| 12057491 | Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates | Dax M. Crum, Stephen M. Cea, Leonard P. GULER, Tahir Ghani | 2024-08-06 |
| 12014959 | Integrated nanowire and nanoribbon patterning in transistor manufacture | Leonard P. GULER, Mark Armstrong, Tahir Ghani, William Hsu | 2024-06-18 |
| 12002810 | Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up approach | Dax M. Crum, Leonard P. GULER, Tahir Ghani | 2024-06-04 |
| 11990472 | Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates | Leonard P. GULER, Michael K. Harper, William Hsu, Tahir Ghani, Niels Zussblatt +6 more | 2024-05-21 |
| 11984449 | Channel structures with sub-fin dopant diffusion blocking layers | Cory Bomberger, Anand S. Murthy, Stephen M. Cea, Anupama Bowonder, Tahir Ghani | 2024-05-14 |
| 11929396 | Cavity spacer for nanowire transistors | William Hsu, Leonard P. GULER, Souvik Chakrabarty, Jun Sung Kang, Bruce Beattie +1 more | 2024-03-12 |
| 11908856 | Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact | William Hsu, Chung-Hsun Lin, Kinyip Phoa, Oleg Golonzka, Tahir Ghani +5 more | 2024-02-20 |
| 11901458 | Dielectric isolation layer between a nanowire transistor and a substrate | Bruce Beattie, Leonard P. GULER, Jun Sung Kang, William Hsu | 2024-02-13 |
| 11894368 | Gate-all-around integrated circuit structures fabricated using alternate etch selective material | Sudipto Naskar, William Hsu, Bruce Beattie, Tahir Ghani | 2024-02-06 |
| 11869891 | Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process | Jun Sung Kang, Kai Loon Cheong, Erica J. Thompson, William Hsu, Dax M. Crum +2 more | 2024-01-09 |
| 11869987 | Gate-all-around integrated circuit structures including varactors | Ayan Kar, Saurabh Morarka, Carlos Nieva-Lozano, Kalyan C. Kolluru, Chung-Hsun Lin +2 more | 2024-01-09 |
| 11869973 | Nanowire transistor structure and method of shaping | Erica J. Thompson, Aditya Kasukurti, Jun Sung Kang, Kai Loon Cheong, William Hsu +1 more | 2024-01-09 |
| 11862635 | Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions | Leonard P. GULER, Tahir Ghani, Swaminathan Sivakumar | 2024-01-02 |