Issued Patents 2024
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12114479 | Three-dimensional memory arrays with layer selector transistors | Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa +2 more | 2024-10-08 |
| 12033894 | Gate aligned contact and method to fabricate same | Oleg Golonzka, Charles H. Wallace, Tahir Ghani | 2024-07-09 |
| 11972979 | 1D vertical edge blocking (VEB) via and plug | Leonard P. GULER, Michael K. Harper, Suzanne S. Rich, Charles H. Wallace, Curtis W. Ward +4 more | 2024-04-30 |
| 11862635 | Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions | Leonard P. GULER, Biswajeet Guha, Tahir Ghani | 2024-01-02 |