Issued Patents 2024
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12132079 | Bonding and isolation techniques for stacked transistor structures | Kuan-Kan Hu, Han-De Chen, Ku-Feng Yang, Chen-Fong Tsai, Chi On Chui | 2024-10-29 |
| 12131954 | Selective epitaxy process for the formation of CFET local interconnection | Che Chi Shih, Hsin Yang Hung, Ku-Feng Yang, Wei-Yen Woon | 2024-10-29 |
| 12119271 | Backside gate contact, backside gate etch stop layer, and methods of forming same | Yi-Bo Liao, Wei-De Ho, Cheng-Ting Chung | 2024-10-15 |
| 12094955 | Confined epitaxial regions for semiconductor devices | Michael L. Hattendorf, Tahir Ghani | 2024-09-17 |
| 12027417 | Source or drain structures with high germanium concentration capping layer | Cory Bomberger, Suresh Vishwanath, Yulia Tolstova, Pratik A. Patel, Anand S. Murthy | 2024-07-02 |
| 11984506 | Field effect transistor having a gate dielectric with a dipole layer and having a gate stressor layer | Vishal Tiwari, Rishabh Mehandru, Dan S. LAVRIC, Michal Mleczko | 2024-05-14 |
| 11908940 | Field effect transistor with a hybrid gate spacer including a low-k dielectric material | Pratik A. Patel | 2024-02-20 |
| 11901457 | Fin shaping and integrated circuit structures resulting therefrom | Rahul Pandey, Rishabh Mehandru, Anupama Bowonder, Pratik A. Patel | 2024-02-13 |
| 11887860 | Mid-processing removal of semiconductor fins during fabrication of integrated circuit structures | Mehmet O. Baykan, Anurag Jain | 2024-01-30 |
| 11869889 | Self-aligned gate endcap (SAGE) architectures without fin end gap | Scott B. Clendenning, Jessica M. Torres, Lukas Baumgartel, Kiran CHIKKADI, Diane LANCASTER +4 more | 2024-01-09 |