Issued Patents 2024
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12159869 | Backside interconnect structures for semiconductor devices and methods of forming the same | Hou-Yu Chen, Ching-Wei Tsai | 2024-12-03 |
| 12154960 | Semiconductor device and manufacturing method thereof | Hou-Yu Chen, Ching-Wei Tsai | 2024-11-26 |
| 12148837 | Semiconductor devices | Yi-Bo Liao, Yu-Xuan Huang, Pei-Yu Wang, Ching-Wei Tsai, Hou-Yu Chen | 2024-11-19 |
| 12119271 | Backside gate contact, backside gate etch stop layer, and methods of forming same | Yi-Bo Liao, Wei-De Ho, Szuya S. Liao | 2024-10-15 |
| 12094938 | Semiconductor device with low resistances and methods of forming such | Yu-Xuan Huang, Wang-Chun Huang, Yi-Bo Liao, Hou-Yu Chen, Kuan-Lun Cheng +1 more | 2024-09-17 |
| 12068370 | Semiconductor device structure and methods of forming the same | Chi-Yi Chuang, Hou-Yu Chen, Kuan-Lun Cheng | 2024-08-20 |
| 12046681 | Gate-all-around structure with self substrate isolation and methods of forming the same | Ching-Wei Tsai, Kuan-Lun Cheng | 2024-07-23 |
| 12009293 | Barrier-free interconnect structure and manufacturing method thereof | Pei-Yu Wang, Wei Ju Lee | 2024-06-11 |
| 11948989 | Gate-all-around device with protective dielectric layer and method of forming the same | Yi-Bo Liao, Hou-Yu Chen, Kuan-Lun Cheng | 2024-04-02 |
| 11908942 | Transistors having nanostructures | Ching-Wei Tsai, Kuan-Lun Cheng | 2024-02-20 |
| 11862701 | Stacked multi-gate structure and methods of fabricating the same | Hou-Yu Chen, Kuan-Lun Cheng | 2024-01-02 |