Issued Patents 2023
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854884 | Fully aligned top vias | Nicholas Anthony Lanzillo, Somnath Ghosh, Christopher J. Penny, Robert R. Robison, Lawrence A. Clevenger | 2023-12-26 |
| 11848264 | Semiconductor structure with stacked vias having dome-shaped tips | Kenneth Chun Kuen Cheng, Chanro Park, Alexander Reznicek | 2023-12-19 |
| 11798842 | Line formation with cut-first tip definition | Chanro Park, Hsueh-Chung Chen, Yann Mignot | 2023-10-24 |
| 11791290 | Physical unclonable function for secure integrated hardware systems | Oscar van der Straten, Ruilong Xie, Alexander Reznicek | 2023-10-17 |
| 11758819 | Magneto-resistive random access memory with laterally-recessed free layer | Oscar van der Straten, Kenneth Chun Kuen Cheng, Joseph F. Maniscalco, Chih-Chao Yang | 2023-09-12 |
| 11735475 | Removal of barrier and liner layers from a bottom of a via | Chanro Park, Kenneth Chun Kuen Cheng, Nicholas Anthony Lanzillo | 2023-08-22 |
| 11735468 | Interconnect structures including self aligned vias | Chih-Chao Yang, Terry A. Spooner, Shyng-Tsong Chen | 2023-08-22 |
| 11682471 | Dual damascene crossbar array for disabling a defective resistive switching device in the array | Joseph F. Maniscalco, Oscar van der Straten, Choonghyun Lee, Seyoung Kim | 2023-06-20 |
| 11664271 | Dual damascene with short liner | Oscar van der Straten, Joseph F. Maniscalco, Alexander Reznicek, Raghuveer R. Patlolla, Theodorus E. Standaert | 2023-05-30 |
| 11637036 | Planarization stop region for use with low pattern density interconnects | Cornelius Brown Peethala, Hari Prasad Amanapu, Raghuveer R. Patlolla, Chih-Chao Yang | 2023-04-25 |