Issued Patents 2020
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879629 | Method of electroplating metal into recessed feature and electroplating layer in recessed feature | Jun-Nan Nian, Jyun-Ru Wu, Shiu-Ko JangJian, Yu-Ren PENG, Yu-Sheng Wang | 2020-12-29 |
| 10867845 | Semiconductor device and method | Yu-Sheng Wang, Ching-Hwanq Su, Liang-Yueh Ou Yang, Ming-Hsing Tsai, Yu-Ting Lin | 2020-12-15 |
| 10840184 | Formation of copper layer structure with self anneal strain improvement | Jun-Nan Nian, Shiu-Ko JangJian, Yu-Sheng Wang, Hung-Hsu Chen | 2020-11-17 |
| 10840330 | Block layer in the metal gate of MOS devices | Jung-Chih Tsao, Yu-Sheng Wang, Wen-Hsi Lee, Kei-Wei Chen, Ying-Lang Wang | 2020-11-17 |
| 10832974 | FinFET gate structure and method for fabricating the same | Shiu-Ko JangJian, Horng-Huei Tseng | 2020-11-10 |
| 10833196 | FinFET structures and methods of forming the same | Yu-Sheng Wang, Chia-Ching Lee, Chung-Chiang Wu, Ching-Hwanq Su | 2020-11-10 |
| 10755938 | Metal gate and manufacturing method thereof | Yu-Sheng Wang, Ting-Siang Su, Ching-Hwanq Su | 2020-08-25 |
| 10749278 | Method of electroplating metal into recessed feature and electroplating layer in recessed feature | Jun-Nan Nian, Jyun-Ru Wu, Shiu-Ko JangJian, Yu-Ren PENG, Yu-Sheng Wang | 2020-08-18 |
| 10714576 | Semiconductor device and method for manufacturing the same | Kei-Wei Chen, Yu-Sheng Wang, Ming-Ching CHUNG, Chia-Yang Wu | 2020-07-14 |
| 10714357 | Methods for improved critical dimension uniformity in a semiconductor device fabrication process | Chun-Kuang Chen, De-Fang Chen, Wei-Liang Lin, Yu-Tien Shen | 2020-07-14 |
| 10692725 | Directed self-assembly process with size-restricted guiding patterns | Ming-Huei Weng, Kuan-Hsin Lo, Wei-Liang Lin | 2020-06-23 |
| 10658184 | Pattern fidelity enhancement with directional patterning technology | Yu-Tien Shen, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting +7 more | 2020-05-19 |