Issued Patents 2020
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10854733 | Composite spacer enabling uniform doping in recessed fin devices | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2020-12-01 |
| 10840329 | Nanosheet transistor having improved bottom isolation | Ruilong Xie, Kangguo Cheng | 2020-11-17 |
| 10833198 | Confined source drain epitaxy to reduce shorts in CMOS integrated circuits | Ruilong Xie, Lan Yu, Alexander Reznicek | 2020-11-10 |
| 10833155 | Vertical field effect transistor with top and bottom airgap spacers | Veeraraghavan S. Basker, Junli Wang, Alexander Reznicek | 2020-11-10 |
| 10818776 | Nanosheet transistor with optimized junction and cladding detectivity control | Kangguo Cheng, Nicolas Loubet, Ruilong Xie, Tenko Yamashita | 2020-10-27 |
| 10804270 | Contact formation through low-tempearature epitaxial deposition in semiconductor devices | Oleg Gluschenkov, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita | 2020-10-13 |
| 10804136 | Fin structures with bottom dielectric isolation | Kangguo Cheng, Tenko Yamashita, Ruilong Xie | 2020-10-13 |
| 10784365 | Fin field effect transistor fabrication and devices having inverted T-shaped gate | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2020-09-22 |
| 10784357 | Fabrication of vertical field effect transistor structure with controlled gate length | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2020-09-22 |
| 10777465 | Integration of vertical-transport transistors and planar transistors | Ruilong Xie, Kangguo Cheng, Tenko Yamashita | 2020-09-15 |
| 10749031 | Large area contacts for small transistors | Xiuyu Cai, Qing Liu, Ruilong Xie | 2020-08-18 |
| 10714470 | Method and apparatus of forming high voltage varactor and vertical transistor on a substrate | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2020-07-14 |
| 10692868 | Contact formation through low-temperature epitaxial deposition in semiconductor devices | Oleg Gluschenkov, Shogo Mochizuki, Hiroaki Niimi, Tenko Yamashita | 2020-06-23 |
| 10680081 | Vertical transistors with improved top source/drain junctions | Kangguo Cheng, Muthumanickam Sankarapandian, Ruilong Xie, Tenko Yamashita | 2020-06-09 |
| 10680064 | Techniques for VFET top source/drain epitaxy | Kangguo Cheng, Cheng Chi, Chi-Chun Liu, Ruilong Xie, Tenko Yamashita | 2020-06-09 |
| 10629709 | Punch through stopper in bulk finFET device | Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita | 2020-04-21 |
| 10622357 | FinFET including tunable fin height and tunable fin width ratio | Xiuyu Cai, Qing Liu, Ruilong Xie | 2020-04-14 |
| 10622457 | Forming replacement low-K spacer in tight pitch fin field effect transistors | Xiuyu Cai, Qing Liu, Ruilong Xie | 2020-04-14 |
| 10615277 | VFET CMOS dual epitaxy integration | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2020-04-07 |
| 10600778 | Method and apparatus of forming high voltage varactor and vertical transistor on a substrate | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2020-03-24 |
| 10593780 | Forming replacement low-K spacer in tight pitch fin field effect transistors | Xiuyu Cai, Qing Liu, Ruilong Xie | 2020-03-17 |
| 10580854 | High thermal budget compatible punch through stop integration using doped glass | Kangguo Cheng, Sanjay C. Mehta, Xin Miao | 2020-03-03 |
| 10580855 | High thermal budget compatible punch through stop integration using doped glass | Kangguo Cheng, Sanjay C. Mehta, Xin Miao | 2020-03-03 |
| 10566442 | Vertical field effect transistor with reduced parasitic capacitance | Kangguo Cheng, Ruilong Xie, Tenko Yamashita | 2020-02-18 |
| 10566454 | Self-aligned contact process enabled by low temperature | Hong He, Chiahsun Tseng, Yunpeng Yin | 2020-02-18 |