Issued Patents 2020
Showing 101–125 of 132 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10585063 | Superhydrophobic electrode and biosensing device using the same | Ali Afzali-Ardakani, Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi, Bahman Hekmatshoartabari | 2020-03-10 |
| 10580901 | Stacked series connected VFETs for high voltage applications | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2020-03-03 |
| 10580977 | Tightly integrated 1T1R ReRAM for planar technology | Takashi Ando, Pouya Hashemi | 2020-03-03 |
| 10580966 | Faceted sidewall magnetic tunnel junction structure | Oscar van der Straten, Praneet Adusumilli | 2020-03-03 |
| 10573596 | FinFET fuses formed at tight pitch dimensions | Oscar van der Straten, Praneet Adusumilli, Bahman Hekmatshoartabari | 2020-02-25 |
| 10573723 | Vertical transport FETs with asymmetric channel profiles using dipole layers | Takashi Ando, Choonghyun Lee, Sanghoon Shin, Jingyun Zhang, Pouya Hashemi | 2020-02-25 |
| 10573648 | Low voltage (power) junction FET with all-around junction gate | Karthik Balakrishnan, Bahman Hekmatshoartabari, Jeng-Bang Yau | 2020-02-25 |
| 10573521 | Gate metal patterning to avoid gate stack attack due to excessive wet etching | Junli Wang, Shogo Mochizuki, Joshua M. Rubin | 2020-02-25 |
| 10566349 | FinFET with stacked faceted S/D epitaxy for improved contact resistance | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2020-02-18 |
| 10566447 | Single column compound semiconductor bipolar junction transistor with all-around base | Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning | 2020-02-18 |
| 10566240 | Wimpy device by selective laser annealing | Kangguo Cheng, Nicolas Loubet, Xin Miao | 2020-02-18 |
| 10559672 | Vertical transport field-effect transistor including dual layer top spacer | Hemanth Jagannathan, Choonghyun Lee, Christopher J. Waskiewicz | 2020-02-11 |
| 10559692 | Nanosheet substrate isolation scheme by lattice matched wide bandgap semiconductor | Xin Miao, Jingyun Zhang, Choonghyun Lee | 2020-02-11 |
| 10559671 | Vertical transport field-effect transistor including air-gap top spacer | Hemanth Jagannathan, Choonghyun Lee, Christopher J. Waskiewicz | 2020-02-11 |
| 10553678 | Vertically stacked dual channel nanosheet devices | Choonghyun Lee, Jingyun Zhang, Pouya Hashemi, Takashi Ando | 2020-02-04 |
| 10553708 | Twin gate tunnel field-effect transistor (FET) | Karthik Balakrishnan, Bahman Hekmatshoartabari, Jeng-Bang Yau | 2020-02-04 |
| 10553696 | Full air-gap spacers for gate-all-around nanosheet field effect transistors | Takashi Ando, Pouya Hashemi, Choonghyun Lee, Jingyun Zhang | 2020-02-04 |
| 10553679 | Formation of self-limited inner spacer for gate-all-around nanosheet FET | Jingyun Zhang, Takashi Ando, Choonghyun Lee, Pouya Hashemi | 2020-02-04 |
| 10553586 | Stacked complementary junction FETs for analog electronic circuits | Karthik Balakrishnan, Bahman Hekmatshoartabari, Jeng-Bang Yau | 2020-02-04 |
| 10546857 | Vertical transistor transmission gate with adjacent NFET and PFET | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2020-01-28 |
| 10546928 | Forming stacked twin III-V nano-sheets using aspect-ratio trapping techniques | Pouya Hashemi, Karthik Balakrishnan, Mahmoud Khojasteh | 2020-01-28 |
| 10546925 | Vertically stacked nFET and pFET with dual work function | Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi | 2020-01-28 |
| 10546918 | Multilayer buried metal-insultor-metal capacitor structures | Joshua M. Rubin, Oscar van der Straten, Praneet Adusumilli | 2020-01-28 |
| 10546915 | Buried MIM capacitor structure with landing pads | Praneet Adusumilli, Oscar van der Straten, Joshua M. Rubin | 2020-01-28 |
| 10546815 | Low resistance interconnect structure with partial seed enhancement liner | Oscar van der Straten, Joseph F. Maniscalco, Koichi Motoyama | 2020-01-28 |