Issued Patents 2020
Showing 51–75 of 132 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10727070 | Liner-less contact metallization | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2020-07-28 |
| 10720502 | Vertical transistors having a layer of charge carriers in the extension region for reduced extension region resistance | Takashi Ando, Pouya Hashemi, Choonghyun Lee, Jingyun Zhang | 2020-07-21 |
| 10720528 | Method and structure of stacked FinFET | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2020-07-21 |
| 10720427 | Diode connected vertical transistor | Karthik Balakrishnan, Pouya Hashemi | 2020-07-21 |
| 10714593 | Fabrication of strained vertical p-type field effect transistors by bottom condensation | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2020-07-14 |
| 10714570 | Fabrication of perfectly symmetric gate-all-around FET on suspended nanowire using interface interaction | Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz | 2020-07-14 |
| 10707304 | Vertically stacked nFET and pFET with dual work function | Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi | 2020-07-07 |
| 10707332 | FinFET with epitaxial source and drain regions and dielectric isolated channel region | Kangguo Cheng, Ramachandra Divakaruni, Ali Khakifirooz, Soon-Cheon Seo | 2020-07-07 |
| 10700058 | Compound semiconductor devices having buried resistors formed in buffer layer | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2020-06-30 |
| 10692859 | Large area diode co-integrated with vertical field-effect-transistors | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2020-06-23 |
| 10692866 | Co-integrated channel and gate formation scheme for nanosheet transistors having separately tuned threshold voltages | Takashi Ando, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi | 2020-06-23 |
| 10692722 | Single process for linear and metal fill | Praneet Adusumilli, Oscar van der Straten, Chih-Chao Yang | 2020-06-23 |
| 10679890 | Nanosheet structure with isolated gate | Xin Miao, Joshua M. Rubin | 2020-06-09 |
| 10680085 | Transistor structure with varied gate cross-sectional area | Dominic J. Schepis, Pranita Kerber, Qiqing C. Ouyang | 2020-06-09 |
| 10672862 | High density vertically integrated FEOL MIM capacitor | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2020-06-02 |
| 10672490 | One-time-programmable memory in a high-density three-dimensional structure | Bahman Hekmatshoartabari | 2020-06-02 |
| 10672865 | Deformable and flexible capacitor | Karthik Balakrishnan, Stephen W. Bedell, Pouya Hashemi | 2020-06-02 |
| 10665541 | Biconvex low resistance metal wire | Praneet Adusumilli, Oscar van der Straten | 2020-05-26 |
| 10658513 | Formation of FinFET junction | Kevin K. Chan, Pouya Hashemi, Ali Khakifirooz, John A. Ott | 2020-05-19 |
| 10658353 | Stacked electrostatic discharge diode structures | Bahman Hekmatshoartabari, Karthik Balakrishnan, Tak H. Ning | 2020-05-19 |
| 10658494 | Transistors and methods of forming transistors using vertical nanowires | Dominic J. Schepis | 2020-05-19 |
| 10658462 | Vertically stacked dual channel nanosheet devices | Choonghyun Lee, Jingyun Zhang, Pouya Hashemi, Takashi Ando | 2020-05-19 |
| 10658429 | High-density field-enhanced ReRAM integrated with vertical transistors | Takashi Ando, Pouya Hashemi | 2020-05-19 |
| 10658507 | Vertical transistor pass gate device | Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi | 2020-05-19 |
| 10651089 | Low thermal budget top source and drain region formation for vertical transistors | Shogo Mochizuki, Oleg Gluschenkov | 2020-05-12 |